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rx64m group renesas mcus datasheet r01ds0173ej0100 rev.1.00 page 1 of 230 jul 31, 2014 features 32-bit rxv2 cpu core ? max. operating frequency: 120 mhz capable of 240 dmips in operation at 120 mhz ? single precision 32-bit ieee-754 floating point ? two types of multiply-and-accumula tion unit (between memories and between registers) ? 32-bit multiplier (fastest instruction execution takes one cpu clock cycle) ? divider (fastest instruction execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions: ultra-compact code ? supports the memory protection unit (mpu) ? jtag and fine (two-line) debugging interfaces low-power design and architecture ? operation from a single 2.7- to 3.6-v supply ? low power consumption: a product that supports all peripheral functions draws only 0.3ma/mhz (typ.). ? rtc is capable of operation from a dedicated power supply. ? four low-power modes on-chip code flash memory, no wait states ? supports versions with up to 4 mbytes of rom ? 120-mhz operation, 8.3-ns read cycle (no wait states) ? user code is programmable by on -board or off-board programming. ? programming/erasing as background operations (bgos) on-chip data flash memory ? 64 kbytes, reprogrammable up to 100,000 times ? programming/erasing as background operations (bgos) on-chip sram ? 512 kbytes of sram (no wait states) ? 32 kbytes of ram with ecc (one wait state, single-error correction and double error detection) ? 8 kbytes of standby ram (backup on deep software standby) data transfer ? dmac: 8 channels ? dtc ? exdmac: 2 channels ? dmac for the ethernet controller: 3 channels for 176- and 177-pin products; 2 channels for 100-, 144-, and 145-pin products reset and supply management ? power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external crystal oscillator or internal pll for operation at 8 to 24 mhz ? internal 240-khz loco and hoco selectable from 16, 18, and 20 mhz ? 120-khz clock for the iwdta real-time clock ? adjustment functions (30 seconds, leap year, and error) ? real-time clock counting and binary counting modes are selectable ? time capture function (for capturing times in response to event-signal input) independent watchdog timer ? 120-khz (1/2 loco frequency) clock operation useful functions for iec60730 compliance ? oscillation-stoppage detection, frequency measurement, crc, iwdta, self-diagnostic functio n for the a/d converter, etc. ? register write protection function can protect values in important registers against overwriting. various communications interfaces ? ieee 1588-compliant ethernet mac (for 176- and 177-pin products: 2 modules) ? phy layer for host/function or ot g controller (1) with full-speed usb 2.0 with battery charging transfer (only for 176- and 177-pin products) ? phy layer (1) for host/function or otg controller (1) with full- speed usb 2.0 transfer ? can (compliant with iso11898-1), incorporating 32 mailboxes (up to 3 modules) ? scig and scih with multiple functionalities (up to 9) choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, si mplified spi, simplified i 2 c, and extended serial mode. ? scifa with 16-byte transmission and reception fifos (up to 4 interfaces) ? i 2 c bus interface for transfer at up to 1 mbps (up to 2 interfaces) ? four-wire qspi (1 interface) in addition to rspia (1 interface) ? parallel data capture unit (pdc) fo r the cmos camera interface (not in 100-pin products) ? sd host interface (optional: 1 interface) with a 1- or 4-bit sd bus for use with sd memory or sdio external address space ? buses for full-speed data transfer (max. operating frequency of 60 mhz) ? 8 cs areas ? 8-, 16-, or 32-bit bus space is selectable per area ? independent sdram area (128 mbytes) up to 29 extended-function timers ? 16-bit tpua, mtu3a, and gpta: input capture, output compare, pwm waveform output ? 8-bit tmra (4 channels), 16-bit cm t (4 channels), 32-bit cmtw (2 channels) 12-bit a/d converter ? two 12-bit units (8 channels fo r unit 0; 21 channels for unit 1) ? self diagnosis ? detection of analog input disconnection 12-bit d/a converter: 2 channels ? on-chip operational amplifier output or direct input selectable temperature sensor for measuring temperature within the chip encryption (optional) ? aes (key lengths: 128, 196, and 256 bits) ? des (key lengths: 56 bits (d es); 3 56 bits (t-des)) ? sha (sha-1 (128), sha-2 (224 or 256), hmac (160, 224, or 256)) up to 127 pins for general i/o ports ? 5-v tolerance, open drain, input pull-up, switchable driving ability operating temp. range ? ?40 ? c to +85 ? c plqp0176kb-a 24 24 mm, 0.5-mm pitch plqp0144ka-a 20 20 mm, 0.5-mm pitch plqp0100kb-a 14 14 mm, 0.5-mm pitch ptlg0177ka-a 8 8 mm, 0.5-mm pitch ptlg0145ka-a 7 7 mm, 0.5-mm pitch ptlg0100ja-a 7 7 mm, 0.65-mm pitch plbg0176ga-a 13 13mm, 0.8-mm pitch 120-mhz 32-bit rx mcu, on-chip fpu, 240 dmips, up to 4-mb flash memory, 512-kb sram, various communications interfaces including ieee 1588-compliant ethernet mac, full-speed usb 2.0 with battery charging, sd host interface (optional), quad spi, and can, 12-bit a/d converter, rtc, encryption (optional), serial interface for audio, cmos camera interface r01ds0173ej0100 rev.1.00 jul 31, 2014 features
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 2 of 230 jul 31, 2014 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 shows the outline of maximum specifications, and th e number of peripheral module channels differs depending on the pin number on the package and th e code flash memory cap acity. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/9) classification module/function description cpu cpu ? maximum operating frequency: 120 mhz ? 32-bit rx cpu (rxv2) ? minimum instruction execution time: one in struction per state (cycle of the system clock) ? address space: 4-gbyte linear ? register set of the cpu general purpose: sixteen 32-bit registers control: ten 32-bit registers accumulator: two 72-bit registers ? basic instructions: 75 ? floating-point instructions: 11 ? dsp instructions: 23 ? addressing modes: 11 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 32 64 bits ? on-chip divider: 32 / 32 32 bits ? barrel shifter: 32 bits fpu ? single precision (32-bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory code flash memory ? capacity: 2 mbytes, 2.5 mbytes, 3 mbytes, 4 mbytes ? 120 mhz, no-wait access ? on-board programming: four types ? off-board programming (parallel programmer mode) ? the trusted memory (tm) function protects against the reading of programs from blocks 8 and 9. data flash memory ? capacity: 64 kbytes ? programming/erasing: 100,000 times ram ? capacity: 512 kbytes ? 120 mhz, no-wait access ram with ecc ? capacity: 32 kbytes ? 120 mhz, single wait access ? sec-ded (single error correction/double error detection) standby ram ? capacity: 8 kbytes ? operation synchronized with pclkb: up to 60 mhz, two-cycle access operating modes ? operating modes by the mode-se tting pins at the time of release from the reset state single-chip mode boot mode (for the sci interface) boot mode (for the usb interface) user boot mode ? selection of operating mode by register setting single-chip mode, user boot mode on-chip rom disabled extended mode on-chip rom enabled extended mode ? endian selectable
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 3 of 230 jul 31, 2014 clock clock generation circuit ? main clock oscillator, sub clock oscillator , low-speed/high-speed on-chip oscillator, pll frequency synthesizer, and iwdt -dedicated on-chip oscillator ? the peripheral module clocks can be set to frequencies above that of the system clock. ? main-clock oscillat ion stoppage detection ? separate frequency-division and multiplication settings fo r the system clock (iclk), peripheral module clocks (pclka, pclkb, pc lkc, pclkd), flash-if clock (fclk) and external bus clock (bclk) the cpu and other bus masters run in synchroni zation with the system clock (iclk): up to 120 mhz peripheral modules of mtu3, gpt, rsp i, scifa, usba, etherc, eptpc, edmac, and aes run in synchronization with pclka, which operates at up to 120 mhz. other peripheral modules run in synchr onization with pclkb: up to 60 mhz adclk in the sd12ad (unit 0) runs in synchronization with pclkc: up to 60 mhz adclk in the sd12ad (unit 1) runs in synchronization with pclkd: up to 60 mhz flash if run in synchronization with t he flash-if clock (fclk): up to 60 mhz devices connected to the external bus run in synchronization with t he external bus clock (bclk): up to 60 mhz ? multiplication is possible with using t he high-speed on-chip oscillator (hoco) as a reference clock of the pll circuit reset nine types of reset ? res# pin reset: generated when the res# pin is driven low. ? power-on reset: generated when the res# pin is driven high and vcc = avcc0 = avcc1 rises. ? voltage-monitoring 0 reset: generated when vcc = avcc0 = avcc1 falls. ? voltage-monitoring 1 reset: generated when vcc = avcc0 = avcc1 falls. ? voltage-monitoring 2 reset: generated when vcc = avcc0 = avcc1 falls. ? deep software standby reset: generated in response to an interrupt to trigger release from deep software standby. ? independent watchdog timer reset: generated when the independent watchdog timer underflows, or a refresh error occurs. ? watchdog timer reset: generated when the watchdog timer underflows, or a refresh error occurs. ? software reset: generated by register setting. power-on reset if the res# pin is at the high level when power is supplied, an internal reset is generated. after vcc = avcc0 = avcc1 has exceeded the voltage detection level and the specified period has elapsed, t he reset is cancelled. voltage detection circuit (lvda) monito rs the voltage being input to the vcc = avcc0 = avcc1 pins and generates an internal reset or internal interrupt. ? voltage detection circuit 0 capable of generating an internal reset the option-setting memory can be used to se lect enabling or disabling of the reset. voltage detection level: selectable from three different levels (2.94 v, 2.87 v, and 2.80 v) ? voltage detection circuits 1 and 2 voltage detection level: selectable from three different levels (2.99 v, 2.92 v, and 2.85 v) digital filtering (1/2, 1/4, 1/8, and 1/16 loco frequency) capable of generating an internal reset ? two types of timing are selectable for release from reset an internal interrupt can be requested. ? detection of voltage rising above and fa lling below thresholds is selectable. ? maskable or non-maskable interrupt is selectable voltage detection monitoring event linking low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode battery backup function ? when the voltage on the vcc pin drops, battery power from the vbatt pin is supplied to keep the real-time clock (rtc) operating. table 1.1 outline of specifications (2/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 4 of 230 jul 31, 2014 interrupt interrupt controller (icua) ? peripheral function interrupts: 293 sources ? external interrupts: 16 (pins irq0 to irq15) ? software interrupts: 2 sources ? non-maskable interrupts: 7 sources ? sixteen levels specifiable for the order of priority ? method of interrupt source selection: the interrupt vectors consist of 256 vectors (128 sources are fixed. the remaining 128 vectors are selected from among the other 156 sources.) external bus extension ? the external address space can be divided into eight areas (cs0 to cs7), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs7) a chip-select signal (cs0# to cs7#) can be output for each area. each area is specifiable as an 8-, 16-, or 32-bit bus space. the data arrangement in each area is selectable as little or big endian (only for data). ? sdram interface connectable ? bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmacaa) ? 8 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external interrupts, and interrupt requests from peripheral functions exdma controller (exdmaca) ? 2 channels four transfer modes: normal transfer, r epeat transfer, block transfer, and cluster transfer ? single-address transfer enabled with the edackn signal ? activation sources: software trigger, external dma requests (edreqn), and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: external interrupts and in terrupt requests from peripheral functions i/o ports programmable i/o ports ? i/o ports for the 177-pin tflga (in planning ), 176-pin lfbga (in planning), and 176-pin lqfp i/o pins: 127 input pin: 1 pull-up resistors: 127 open-drain outputs: 127 5-v tolerance: 19 ? i/o ports for the 145-pin tflg a (in planning) and 144-pin lqfp i/o pins: 111 input pin: 1 pull-up resistors: 111 open-drain outputs: 111 5-v tolerance: 18 ? i/o ports for the 100-pin tflg a (in planning) and 100-pin lqfp i/o pins: 78 input pin: 1 pull-up resistors: 78 open-drain outputs: 78 5-v tolerance: 17 event link controller (elc) ? event signals such as interrupt request signal s can be interlinked with the operation of functions such as timer counting, eliminat ing the need for intervention by the cpu to control the functions. ? 119 internal event signals can be freely co mbined for interlinked operation with connected functions. ? event signals from peripheral modules can be used to change the states of output pins (of ports b and e). ? changes in the states of pins (of ports b and e) being used as inputs can be interlinked with the operation of peripheral modules. table 1.1 outline of specifications (3/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 5 of 230 jul 31, 2014 timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 1 unit ? maximum of 16 pulse-input/output possible ? select from among seven or eight c ounter-input clock signals for each channel ? input capture/output compare function ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counti ng mode (two phase encoder input) and cascade-connected operation (32 bits 2 channels) depending on the channel. ? ppg output trigger can be generated ? capable of generating conversion st art triggers for the a/d converters ? digital filtering of signals from the input capture pins ? event linking by the elc timers multifunction timer pulse unit (mtu3a) ? 9 channels (16 bits 8 chann els, 32 bits 1 channel) ? maximum of 16 pulse-input/output and 3 pulse-input possible ? select from among 13 counter-input clock signals for each channel (pclka/1, pclka/ 2, pclka/4, pclka/8, pclka/16, pclk/a32, pclka/64, pclka/256, pclka/1024, mtclka, mtclkb, mtclkc, mtclkd) 11 of the signals are available for channels 1, 3 and 4, 12 are available for channel 2, and 9 are available for channels 5 to 8. ? input capture function ? 39 output compare/input capture registers ? counter clear operation (synchronous cl earing by compare match/input capture) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter operation ? buffered operation ? support for cascade-connected operation ? 43 interrupt sources ? automatic transfer of register data ? pulse output mode toggle/pwm/complementary pwm/reset-synchronized pwm ? complementary pwm output mode outputs non-overlapping waveforms for controlling 3-phase inverters automatic specification of dead times pwm duty cycle: selectable as any value from 0% to 100% delay can be applied to requests for a/d conversion. non-generation of interrupt requests at peak or trough values of counters can be selected. double buffer configuration ? reset synchronous pwm mode three phases of positive and negative pwm wave forms can be output with desired duty cycles. ? phase-counting mode: 16-bit mode (channe ls 1 and 2); 32-bit mode (channels 1 and 2) ? counter functionality for dead-time compensation ? generation of triggers for a/d converter conversion ? a/d converter start triggers can be skipped ? digital filter function for signals on the i nput capture and external counter clock pins ? ppg output trigger can be generated ? event linking by the elc port output enable 3 (poe3a) ? control of the high-impedance state of the mtu3/gpt's waveform output pins ? 5 pins for input from signal source s: poe0, poe4, poe8, poe10, poe11 ? initiation on detection of short-circuited outputs (detection of simultaneous pwm output to the active level) ? initiation by oscillation-stoppage detection or software ? additional programming of output control target pins is enabled table 1.1 outline of specifications (4/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 6 of 230 jul 31, 2014 timers general pwm timer (gpta) ? 16 bits 4 channels ? counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels ? four clock sources independently selectable for all channels (pclka/1, pclka/4, pclka/8, pclka/16) ? 2 input/output pins per channel ? 2 output compare/input capture registers per channel ? for the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. ? in output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically pwm waveforms. ? registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) ? synchronizable operation of the several counters ? modes of synchronized operation (synchroniz ed, or displaced by desired times for phase shifting) ? generation of dead times in pwm operation ? through combination of three counters, generation of automatic three-phase pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in re sponse to external or internal triggers ? internal trigger sources: output of the internal comparator detection, software, and compare-match ? digital filter function for signals on the input capture and external trigger pins ? event linking by the elc programmable pulse generator (ppg) ? (4 bits 4 groups) 2 units ? pulse output with the mtu or tpu output as a trigger ? maximum of 32 pulse-output possible 8-bit timers (tmrb) ? (8 bits 2 channels) 2 units ? select from among seven internal clock signals (pclkb/1, pclkb/2, pclkb/8, pclkb/32, pclkb/64, pclkb/1024, pclkb/8192) and one external clock signal ? capable of output of pulse trains with desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? generation of triggers for a/d converter conversion ? capable of generating baud-rate clocks for sci5, sci6, and sci12 ? event linking by the elc compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four internal clock signals (pclkb/8, pclkb/32, pclkb/128, pclkb/512) ? event linking by the elc compare match timer w (cmtw) ? (32 bits 1 channel) 2 units ? compare-match, input-capture input, and output-comparison output are available. ? select from among four internal clock signals (pclkb/8, pclkb/32, pclkb/128, pclkb/512) ? interrupt requests can be output in respons e to compare-match, input-capture, and output-comparison events. ? event linking by the elc realtime clock (rtcd) ? clock sources: main clock, sub clock ? selection of the 32-bit binary count in time count/second unit possible ? clock and calendar functions ? interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt ? battery backup operation ? time-capture facility for three values ? event linking by the elc watchdog timer (wdta) ? 14 bits 1 channel ? select from among 6 counter-input clock signals (pclkb/4, pclkb/64, pclkb/128, pclkb/512, pclkb/2048, pclkb/8192) independent watchdog timer (iwdta) ? 14 bits 1 channel ? counter-input clock: iwdt- dedicated on-chip oscillator ? dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 ? window function: the positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). ? event linking by the elc table 1.1 outline of specifications (5/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 7 of 230 jul 31, 2014 communication function ethernet controller (etherc) ? 2 channels ? input and output of ethernet/ieee 802.3 frames ? transfer at 10 or 100 mbps ? full- and half-duplex modes ? mii (media independent interface) or rmii (reduced media independent interface) as defined in ieee 802.3u ? detection of magic packets tm * 1 or output of a "wake-on-lan" signal (wol) ? compliance with flow control as defined in ieee 802.3x standards ? filtering of multicast frames ? direct transfer of frames between two channels by cut-through ptp controller for ethernet controller (eptpc) ? a block compatible with the ieee 1588 standard is connected to the ethernet controller (etherc). ? matching with a time stamp can start counting by mtu3 and the gpt. dma controller for ethernet controller (edmaca) ? 3 channels (the round-robin method determi nes the priority of the channels) 2 channels for etherc; 1 channel for eptpc ? alleviation of cpu load by the descriptor control method ? transmission fifo: 2 kbytes; reception fifo: 4 kbytes usb 2.0 fs host/ function module (usbb) ? includes a udc (usb device contro ller) and transceiver for usb 2.0 fs ? one port ? compliance with the usb 2.0 specification ? transfer rate: full speed (12 mbps), low speed (1.5 mbps) (host only) ? both self-power mode and bus power are supported ? otg (on the go) operation is possible (low-speed is not supported) ? incorporates 2 kbytes of ram as a transfer buffer ? external pull-up and pull-down resistors are not required usb 2.0 fs host/ function module with battery charging (usba) ? includes a udc (usb device contro ller) and transceiver for usb 2.0 fs ? one port (only in 176-pin devices) ? compliance with the usb 2.0 specification ? transfer rate: full speed (12 mbps), low speed (1.5 mbps) (host only) ? both self-power mode and bus power are supported ? otg (on the go) operation is possible (low-speed is not supported) ? incorporates 8.5 kbytes of ram as a transfer buffer ? external pull-up and pull-down resistors are not required serial communications interfaces (scig, scih) ? 9 channels (scig: 8 channels + scih: 1 channel) ? scig serial communications modes: asynchr onous, clock synchronous, and smart-card interface multi-processor function on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input fr om tmr timers for sci5, sci6, and sci12 start-bit detection: level or edge detection is selectable. simple i 2 c simple spi 9-bit transfer mode bit rate modulation double-speed mode event linking by the elc (only on chanel 5) ? scih (the following functions are added to scig) supports the serial communications protoc ol, which contains the start frame and information frame supports the lin format serial communications interface with fifo (scifa) ? 4 channels ? methods of transfer: asyn chronous and clock synchronous ? desired bit rates can be selected from the internal baud rate generators. ? lsb or msb first is selectable. ? both the transmission and reception sections are equipped with 16-byte fifo buffers, allowing continuous transmission and reception. ? bit rate modulation ? double-speed mode table 1.1 outline of specifications (6/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 8 of 230 jul 31, 2014 communication function i 2 c bus interface (riica) ? 2 channels (only channel 0 can be used in fast-mode plus) communication formats i 2 c bus format/smbus format supports the multi-master max. transfer rate: 1 mbps (channel 0) ? event linking by the elc can module (can) ? 3 channels ? compliance with the iso11898-1 specific ation (standard frame and extended frame) ? 32 mailboxes per channel serial peripheral interface (rspia) ? 1 channel ? rspi transfer facility using the mosi (master out, slav e in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables seri al transfer through spi operation (four lines) or clock-synchronous operation (three lines) capable of handling serial transfer as a master or slave ? data formats switching between msb first and lsb first the number of bits in each transfer can be ch anged to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) ? buffered structure double buffers for both transmission and reception ? rspck can be stopped with the receive buffer full for master reception. ? event linking by the elc quad serial peripheral interface (qspi) ? 1 channel ? connectable with serial flash memory equippe d with multiple input and output lines (i.e. for single, dual, or quad operation) ? programmable bit length and selectable acti ve sense and phase of the clock signal ? sequential execution of transfer ? lsb or msb first is selectable. serial sound interface (ssi) ? 2 channels ? full-duplex transfe r is possible (only on channel 0). ? support for multiple audio formats ? support for master or slave operation ? bit clock frequency is selectable fr om four different types (16 fs, 32 fs, 48 fs, and 64 fs). ? support for 8-/16-/18-/20-/22-/24 bit data formats ? internal 8-stage fifo for transmission and reception ? stopping ssiws when data transfer is stopped is selectable. sampling rate converter (src) ? 1 channel ? data formats: 32-bit stereo (16 bits for t he left, 16 bits for the right) and 16-bit monaural. ? input sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 khz ? output sampling rates: 32, 44.1, 48, 8* 2 or 16 khz* 2 sd host interface (sdhi)* 4 ? 1 channel ? transfer speed: supports high-speed mode (3.75mb/s) and default speed mode (3.25mb/s) ? one interface for sd memory and i/o ca rds (supporting 1- and 4-bit sd buses) ? sd specifications part 1: physical layer specification ver.3.01 compliant (ddr not supported) part e1: sdio specification ver. 3.00 ? error checking: crc7 for commands and crc16 for data ? interrupt requests: card access interrupt, sdio access interrupt, card detection interrupt ? dma transfer requests: sd_buf write and sd_buf read ? support for card detection and write protection mmc host interface (mmcif) ? 1 channel ? transfer speed: supports hi gh-speed mode (15mb/s) and default speed mode (10mb/s) ? compliant with jedec standard jesd84-a441 (ddr is not supported) ? interface for multimedia cards (mmcs) ? device buses: support for 1-, 4-, and 8-bit mmc buses ? interrupt requests: card detection interrupt, error/timeout interrupt, normal operation interrupt ? dma transfer requests: ce_data write and ce_data read ? support for card detection, boot operation, high priority interrupt (hpi) table 1.1 outline of specifications (7/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 9 of 230 jul 31, 2014 parallel data capture unit (pdc) ? 1 channel ? acquisition of synchronizati on through external 8-bit horizontal and vertical synchronization signals ? setting of the image size when clipping of the output for a one-frame image is required 12-bit a/d converter (s12adc) ? 12 bits 2 units (unit 0: 8 channels; unit 1: 21 channels) ? 12-bit resolution (switchable between 8, 10, and 12 bits) ? conversion time 0.48 s per channel (for 12-bit conversion) 0.45 s per channel (for 10-bit conversion) 0.42 s per channel (for 8-bit conversion) ? operating mode scan mode (single scan mode, conti nuous scan mode, or group scan mode) group a priority control (only for group scan mode) ? sample-and-hold function common sample-and-hold circuit included in addition, channel-dedicated sample-and-hold function (3ch: in unit 0 only) included ? sampling variable sampling time can be set up for each channel. ? digital comparison method: comparison to detect voltages above or below thresholds and window comparison measurement: comparison of two results of c onversion or comparison of a value in the comparison register and a result of conversion ? self-diagnostic function the self-diagnostic function internally gener ates three analog input voltages (unit 0: vrefl0, vrefh0 1/2, vrefh0; unit 1: avss1, avcc1 1/2, avcc1) ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? three ways to start a/d conversion software trigger, timer (mtu3, gpt, tmr, tpu) trigger, external trigger ? event linking by the elc 12-bit d/a converter (r12da) ? 2 channels ? 12-bit resolution ? output voltage: 0.2 v to avcc1 ?? 0.2 v (amplifier output), 0 v to avcc1 (direct output) ? output via an amplifier or direct output can be selected. ? event linking by the elc temperature sensor ? 1 channel ? relative precision: 1c ? the voltage of the temperature is converted into a digital value by the 12-bit a/d converter (unit 1). safety memory protection unit (mpu) ? protection area: eight areas (max.) can be specified in the range from 0000 0000h to ffff ffffh. ? minimum protection unit: 16 bytes ? reading from, writing to, and enabling the exec ution access can be specified for each area. ? an address exception occurs when the detect ed access is not in the permitted area. trusted memory (tm) function ? protects against the reading of programs from blocks 8 and 9 of the code flash memory ? instruction fetching by the cpu is the only fo rm of access to these areas when the tm function is enabled. register write protection function ? protects important registers from being overwritten for in case a program runs out of control. crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with l sb-first or msb-first communications is selectable main clock oscillation stop function ? main clock oscillation stop detection: available clock frequency accuracy measurement circuit (cac) ? monitors the clock output from the main clo ck oscillator, sub-clock oscillator, low- and high-speed on-chip oscillators, the pll fr equency synthesizer, iwdt-dedicated on-chip oscillator, and pclkb, and generates interrupts when the setting range is exceeded. data operation circuit (doc) ? the function to compare, add, or subtract 16-bit data table 1.1 outline of specifications (8/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 10 of 230 jul 31, 2014 note 1. magic packet tm is a registered trademark of advanced micro devices, inc. note 2. setting is only possible when the input sampling rate 44.1 khz is selected. note 3. the product part number differs accordi ng to whether or not it supports encryption. note 4. the product part number differs according to whet her or not it includes an sdhi (sd host interface). encryption function aes* 3 ? key lengths: 128, 196, and 256 bits ? support for cfb, ofb, and cmac operating modes ? speed of calculations: 128-bi t key length in 22 cycles 192-bit key length in 26 cycles 256-bit key length in 30 cycles ? compliant with fips pub 197 des* 3 ? key lengths: 56 bits (des)/3 56 bits (t-des) ? support for des and triple des ? support for ecb and cbc operating modes ? speed of calculations: 6 cloc k cycles in single des mode 14 clock cycles in triple des mode ? compliant with fips pub 46-3 ? compliant with fips pub 81 sha* 3 ? support for sha-1 (128), sha-2 (224 or 256), and hmac (160, 224, or 256) ? speed of calculations: 50 cl ock cycles in sha-1 mode 42 clock cycles in sha-224 mode 42 clock cycles in sha-256 mode ? compliant with sha as defined in fips pub 180-1 and -2 ? compliant with hmac as defined in fips pub 198 true random number generator (rng)* 3 ? length of random numbers: 16 bits ? generation of random-number-generated interrupts after a number is generated ? random number generation time: 3.6 ms (typ) operating frequency up to 120 mhz power supply voltage vcc = avcc0 = avcc1 = vcc_usb = 2.7 to 3.6 v, 2.7 ? vrefh0 ? avcc0, vcc_usba = avcc_usba = 2.7 to 3.6 v, v batt = 2.0 to 3.6 v operating temperature d-version: ? 40 to +85c g-version: ? 40 to +105c (in planning) package 177-pin tflga (ptlg0177ka-a) (in planning) 176-pin lfbga (plbg0176ga-a) (in planning) 176-pin lqfp (plqp0176kb-a) 145-pin tflga (ptlg0145ka-a) (in planning) 144-pin lqfp (plqp0144ka-a) 100-pin tflga (ptlg0100ja-a) (in planning) 100-pin lqfp (plqp0100kb-a) on-chip debugging system ? e1 emulator (jtag and fine interfaces) ? e20 emulator (jtag interface) table 1.1 outline of specifications (9/9) classification module/function description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 11 of 230 jul 31, 2014 table 1.2 comparison of functions for different packages (1/2) functions rx64m group package 177 pins, 176 pins 145 pins, 144 pins 100 pins external bus external bus width 32 bits 16 bits sdram area controller available not supported dma dma controller ch. 0 to 7 data transfer controller available exdma controller ch. 0 and 1 timers 16-bit timer pulse unit ch. 0 to 5 multi-function timer pulse unit 3 ch. 0 to 8 general-purpose pwm timer ch. 0 to 3 port output enable 3 available programmable pulse generator ch. 0 and 1 8-bit timers ch. 0 to 3 compare match timer ch. 0 to 3 compare match timer w ch. 0 and 1 realtime clock available watchdog timer available independent watchdog timer available communication function ethernet controller ch. 0 and 1 ch. 0 ptp controller for ethernet controller available dmac controller for ethernet ch. 0 and 1 (etherc) ch. 2 (eptpc) ch. 0 (etherc) and 2 (eptpc) usb 2.0 fs host/function module ch. 0 usb 2.0 fs host/function module with battery charging available not supported serial communications interfaces (scig) ch. 0 to 7 ch. 0 to 3, 5 and 6 serial communications interfaces (scih) ch. 12 serial communications interfaces with fifo ch. 8 to 11 ch. 8 and 9 i 2 c bus interfaces ch. 0 and 2 serial peripheral interface ch. 0 can module ch. 0 to 2 ch. 0 and 1 quad serial peripheral interface ch. 0 serial sound interfaces ch. 0 and 1 sampling rate converter available sd host interface ch. 0 mmc host interface ch. 0 parallel data capture un it available not supported 12-bit a/d converter an000 to 007 (unit 0: 8 channels) an100 to 120 (unit 1: 21 channels) an000 to 007 (unit 0: 8 channels) an100 to 113 (unit 1: 14 channels) 12-bit d/a converter ch. 0 and 1 ch. 1 temperature sensor available crc calculator available data operation circuit available clock frequency accuracy m easurement circuit available aes available
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 12 of 230 jul 31, 2014 des available sha available rng available event link controller available table 1.2 comparison of functions for different packages (2/2) functions rx64m group package 177 pins, 176 pins 145 pins, 144 pins 100 pins
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 13 of 230 jul 31, 2014 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part no. table 1.3 list of products (1/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi rx64m r5f564mlcdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfc plqp0176kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfc plqp0176kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfc plqp0176kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfc plqp0176kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfb plqp0144ka-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfb plqp0144ka-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfb plqp0144ka-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfb plqp0144ka-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdfp plqp0100kb-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdfp plqp0100kb-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdfp plqp0100kb-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 14 of 230 jul 31, 2014 rx64m r5f564mfcdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdfp plqp0100kb-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdbg plbg0176ga-a 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdbg plbg0176ga-a 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdbg plbg0176ga-a 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdbg plbg0176ga-a 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlc ptlg0177ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlc ptlg0177ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlc ptlg0177ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlc ptlg0177ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlk ptlg0145ka-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlk ptlg0145ka-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlk ptlg0145ka-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available table 1.3 list of products (2/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 15 of 230 jul 31, 2014 note 1. under planning rx64m r5f564mfcdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlk ptlg0145ka-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mlcdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mlddlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mlgdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mlhdlj ptlg0100ja-a* 1 4 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mjcdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mjddlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mjgdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mjhdlj ptlg0100ja-a* 1 3 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mgcdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mgddlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mggdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mghdlj ptlg0100ja-a* 1 2.5 mbytes 512 kbytes 64 kbytes 120 mhz available available r5f564mfcdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported not supported r5f564mfddlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz not supported available r5f564mfgdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available not supported r5f564mfhdlj ptlg0100ja-a* 1 2 mbytes 512 kbytes 64 kbytes 120 mhz available available table 1.3 list of products (3/3) group part no. package code flash memory capacity ram capacity data flash memory capacity operating frequency (max.) encryption module sdhi
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 16 of 230 jul 31, 2014 figure 1.1 how to read the product part number r5f564mlcdfc package type, number of pins, and pin pitch fc: lqfp/176/0.50 bg: lfbga/176/0.80 lc: tflga/177/0.50 fb: lqfp/144/0.50 lk: tflga/145/0.50 fp: lqfp/100/0.50 lj: tflga/100/0.65 d: operating peripheral temperature: ?40 to +85c g: operating peripheral temperature: ?40 to +105c (in planning) d: encryption module not included, sdhi module included h: encryption module included, sdhi module included c: encryption module not included, sdhi module not included g: encryption module included, sdhi module not included code flash memory, ram, and data flash memory capacity l: 4 mbytes/512 kbytes/64 kbytes j: 3 mbyte/512 kbytes/64 kbytes g: 2.5 mbytes/512 kbytes/64 kbytes f: 2 mbytes/512 kbytes/64 kbytes group name 4m: rx64m group series name rx600 series type of memory f: flash memory version renesas mcu renesas semiconductor product
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 17 of 230 jul 31, 2014 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram aes *1 scifa 4 channels usba rspia mtu3a 8 channels gpta 4 channels eptpc etherc 2 channels external bus bsc clock generation circuit rx cpu code flash memory ram port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port c dtca dmacaa 8 channels icua port d port e port f port g port j mpu edmaca 3 channels ram with ecc operand bus instruction bus internal main bus 1 internal main bus 2 exdmaca temperature sensor 12-bit dac 2 channels riica 2 channels rtcd cmtw 1 channel (unit 1) cmtw 1 channel (unit 0) cmt 2 channels (unit 1) cmt 2 channels (unit 0) tmrb 2 channels (unit 1) tmrb 2 channels (unit 0) ppg (unit 1) ppg (unit 0) tpua 6 channels (unit 0) poe3a can 3 channels usbb 1 port scih 1 channel scig 8 channels crc doc cac iwdta wdta pdc mmcif sdhi *1 qspi rng *1 data flash memory standby ram des *1 sha *1 12-bit adc 21 channels (unit 1) 12-bit adc 8 channels (unit 0) internal peripheral buses 1 to 6 src ssi 2ch etherc: ethernet controller eptpc: ptp controller for ethernet controller edmac: dma controller for ethernet controller icua: interrupt controller dtca: data transfer controller dmacaa: dma controller exdmaca: exdma controller bsc: bus controller wdta: watchdog timer iwdta: independent watchdog timer crc: crc (cyclic redundancy check) calculator sci: serial communications interface scifa: serial communications interface with fifo usbb: usb2.0 fs host/function module usba: usb2.0 fs host/function module with battery charging rspia: serial peripheral interface mpu: memory protection unit qspi: quad serial peripheral interface sdhi: sd host interface *1 mmcif: mmc host interface pdc: parallel data capture unit can: can module mtu3a: multi-function timer pulse unit 3 poe3a: port output enable 3 gpta: general-purpose pwm timer tpua: 16-bit timer pulse unit ppg: programmable pulse generator tmrb: 8-bit timer cmt: compare match timer cmtw: compare match timer w rtcd: realtime clock riica: i 2 c bus interface doc: data operation circuit cac: clock frequency accuracy measurement circuit aes: aes* 1 des: des* 1 sha: sha-256* 1 rng: true random number generator *1 ssi: serial sound interface src: sampling rate converter note 1. optional
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 18 of 230 jul 31, 2014 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/8) classifications pin name i/o description digital power supply vcc input power supply pin. c onnect this pin to the system power supply. connect the pin to vss via a 0.1- f multilayer ceramic capacitor. the capacitor shoul d be placed close to the pin. vcl input connect this pin to vss via a 0.1- f multilayer ceramic capacitor. the capacitor shoul d be placed close to the pin. vss input ground pin. connect it to the system power supply (0 v). vbatt input backup power pin clock xtal output pins for a crystal resonator. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. sdclk output outputs the sdram-dedicated clock. xcout output input/output pins for the s ub clock oscillator. connect a crystal resonator between xcout and xcin. xcin input clock frequency accuracy measurement cacref input reference clock input pi n for the clock frequency accuracy measurement circuit operating mode control md input pins for setting t he operating mode. the signal levels on these pins must not be changed during operation. ub input usb boot mode or user boot mode enable pin upsel input selects the power supply method in usb boot mode. the low level selects self-power mode and the high level selects bus power mode. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. emle input input pin for the on-chip emulator enable signal. when the on- chip emulator is used, this pin should be driven high. when not used, it should be driven low. bscanp input boundary scan enable pin. bo undary scan is enabled when this pin goes high. when not used, it should be driven low. on-chip emulator fined i/o fine interface pin trst# input on-chip emulator or boundary scan pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. trsync output this pin indicates that output from the trdata0 to trdata3 pins is valid. trdata0 to trdata3 output these pins output the trace information. address bus a0 to a23 output output pins for the address data bus d0 to d31 i/o input and output pins for the bidirectional data bus multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 19 of 230 jul 31, 2014 bus control rd# output strobe signal which indicates that reading from the external bus interface space is in progress wr# output strobe signal which indicates that writing to the external bus interface space is in prog ress, in 1-write strobe mode wr0# to wr3# output strobe signals which indicate that either group of data bus pins (d7 to d0, d15 to d8, d23 to d16 and d31 to d24) is valid in writing to the external bus interface space, in byte strobe mode bc0# to bc3# output strobe signals which indicate that either group of data bus pins (d7 to d0, d15 to d8, d23 to d16 and d31 to d24) is valid in access to the external bus interface space, in 1-write strobe mode ale output address latch signal when address/data multiplexed bus is selected wait# input input pin for wait request signal s in access to the external space cs0# to cs7# output select signals for cs areas cke output sdram clock enable signal sdcs# output sdram chip select signal ras# output sdram row address strobe signal cas# output sdram column address strove signal we# output sdram write enable pin dqm0 to dqm3 output sdram i/o data mask enable signals exdma controller edreq0, edreq1 input external dma transfer request pins edack0, edack1 output single addr ess transfer acknowledge signals interrupt nmi input non-maskable interrupt request pin irq0 to irq15 input maskable interrupt request pins multi-function timer pulse unit 3 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins mtic5u, mtic5v mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/dead time compensation input pins mtioc6a, mtioc6b mtioc6c, mtioc6d i/o the tgra6 to tgrd6 input capture input/output compare output/pwm output pins mtioc7a, mtioc7b mtioc7c, mtioc7d i/o the tgra7 to tgrd7 input capture input/output compare output/pwm output pins mtioc8a, mtioc8b mtioc8c, mtioc8d i/o the tgra8 to tgrd8 input capture input/output compare output/pwm output pins mtclka, mtclkb mtclkc, mtclkd input input pins for external clock signals or for phase counting mode clock signals port output enable 3 poe0#, poe4#, poe8#, poe10#, poe11# input input pins for request signals to place the mtu or gpt in the high impedance state table 1.4 pin functions (2/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 20 of 230 jul 31, 2014 general-purpose pwm timer gtioc0a-a/gtioc0a-b/ gtioc0a-c/gtioc0a-d/ gtioc0a-e, gtioc0b-a/gtioc0b-b/ gtioc0b-c/gtioc0b-d/ gtioc0b-e i/o gpt0.gtgra and gpt0.gtgrb input capture input/output compare output/pwm output pins gtioc1a-a/gtioc1a-b/ gtioc1a-c/gtioc1a-d/ gtioc1a-e, gtioc1b-a/gtioc1b-b/ gtioc1b-c/gtioc1b-d/ gtioc1b-e i/o gpt1.gtgra and gpt1.gtgrb input capture input/output compare output/pwm output pins gtioc2a-a/gtioc2a-b/ gtioc2a-c/gtioc2a-d/ gtioc2a-e, gtioc2b-a/gtioc2b-b/ gtioc2b-c/gtioc2b-d/ gtioc2b-e i/o gpt2.gtgra and gpt2.gtgrb input capture input/output compare output/pwm output pins gtioc3a-d/gtioc3a-e, gtioc3b-d/gtioc3b-e i/o gpt3.gtgra and gpt3.gtgrb input capture input/output compare output/pwm output pins gtetrg-b/gtetrg-c/ gtetrg-d input external trigger input pin for gpt0 to gpt3 16-bit timer pulse unit tioca0, tiocb0 tiocc0, tiocd0 i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins tioca1, tiocb1 i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins tioca2, tiocb2 i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins tioca3, tiocb3 tiocc3, tiocd3 i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins tioca4, tiocb4 i/o the tgra4 and tgrb4 input capture input/output compare output/pwm output pins tioca5, tiocb5 i/o the tgra5 and tgrb5 input capture input/output compare output/pwm output pins tclka, tclkb tclkc, tclkd input input pins for external clock signals or for phase counting mode clock signals programmable pulse generator po0 to po31 output output pins for the pulse signals 8-bit timer tmo0 to tmo3 output compare match output pins tmci0 to tmci3 input input pins for exter nal clocks to be input to the counter tmri0 to tmri3 input input pins for the counter reset compare match timer w tic0 to tic3 input input pins for cmtw toc0 to toc3 output output pins for cmtw table 1.4 pin functions (3/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 21 of 230 jul 31, 2014 serial communications interface (scig) ? asynchronous mode/cl ock synchronous mode sck0 to sck7 i/o input/output pins for the clock rxd0 to rxd7 input input pins for received data txd0 to txd7 output output pins for transmitted data cts0# to cts7# input input pins for control ling the start of transmission and reception rts0# to rts7# output output pins for c ontrolling the start of transmission and reception ? simple i 2 c mode sscl0 to sscl7 i/o input/output pins for the i 2 c clock ssda0 to ssda7 i/o input/output pins for the i 2 c data ? simple spi mode sck0 to sck7 i/o input/output pins for the clock smiso0 to smiso7 i/o input/output pins for slave transmission of data smosi0 to smosi7 i/o input/output pins for master transmission of data ss0# to ss7# input chip-select input pins serial communications interface (scih) ? asynchronous mode/cl ock synchronous mode sck12 i/o input/output pin for the clock rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling the start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmission of data smosi12 i/o input/output pin for master transmission of data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for received data txdx12 output output pin for transmitted data siox12 i/o input/output pin for received or transmitted data serial communications interface with fifo (scifa) sck8 to sck11 i/o input/output pins for the clock rxd8 to rxd11 input input pins for received data txd8 to txd11 output output pins for transmitted data cts8# to cts11# input input pins for control ling the start of transmission and reception rts8# to rts11# output output pins for controlling the start of transmission and reception i 2 c bus interface scl0[fm+], scl2 i/o input/output pins for clocks. bus can be dire ctly driven by the n- channel open drain sda0[fm+], sda2 i/o input/output pins for data. bus can be directly driven by the n- channel open drain table 1.4 pin functions (4/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 22 of 230 jul 31, 2014 ethernet controller ref50ck0, ref50ck1 input 50-mhz refe rence clocks. these pins input reference signals for transmission/reception timings in rmii mode. rmii0_crs_dv, rmii1_crs_dv input indicate that there are carrier detection signals and valid receive data on rmii_rxd1 and rmii_rxd0 in rmii mode. rmii0_txd0, rmii0_txd1, rmii1_txd0, rmii1_txd1 output 2-bit transmit data in rmii mode rmii0_rxd0, rmii0_rxd1, rmii1_rxd0, rmii1_rxd1 input 2-bit receive data in rmii mode rmii0_txd_en, rmii1_txd_en output output pins for data tr ansmit enable signals in rmii mode rmii0_rx_er, rmii1_rx_er input indicate an error has occurred during reception of data in rmii mode. et0_crs, et1_crs input carrier detection/data reception enable pins et0_rx_dv, et1_rx_dv input indicate that there are valid receive data on et_erxd3 to et_erxd0. et0_exout, et1_exout output general-purpose external output pins et0_linksta et1_linksta input input link status from the phy-lsi. et0_etxd0 to et0_etxd3, et1_etxd0 to et1_etxd3 output 4 bits of mii transmit data et0_erxd0 to et0_erxd3, et1_erxd0 to et1_erxd3 input 4 bits of mii receive data et0_tx_en, et1_tx_en output transmit enable pins. functi on as signals indicating that transmit data is ready on et_etxd3 to et_etxd0. et0_tx_er, et1_tx_er output transmit error pins. function as signals notifying the phy-lsi of an error during transmission. et0_rx_er, et1_rx_er input receive error pins. function as signals to recognize an error during reception. et0_tx_clk, et1_tx_clk input transmit clock pins. these pi ns input reference signals for output timings from et_tx_en, et_etxd3 to et_etxd0, and et_tx_er. et0_rx_clk, et1_rx_clk input receive clock pins. these pins input reference signals for input timings to et_rx_dv, et_erxd3 to et_erxd0, and et_rx_er. et0_col, et1_col input input collision detection signals. et0_wol, et1_wol output receive magic packets. et0_mdc, et1_mdc output output reference clock signals for information transfer via et_mdio. et0_mdio, et1_mdio i/o input or output bidirectional signals for exchange of management information between this mcu and the phy-lsi. table 1.4 pin functions (5/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 23 of 230 jul 31, 2014 usb 2.0 host/function module vcc_usb, vcc_usba input power supply pins vss_usb, vss1_usba, vss2_usba input ground pins avcc_usba input usba analog power supply pin avss_usba input usba analog ground pin. short this pin with the pvss_usba pin. pvss_usba input usba pll circuit ground pin. short this pin with the avss_usba pin. usba_rref i/o usba reference current supply pin. connect 2.2 k ? (1%) to the avss_usba pin. usb0_dp, usba_dp i/o input or output usb transceiver d+ data. usb0_dm, usba_dm i/o input or output usb transceiver d- data. usb0_exicen, usba_exicen output connect to the otg power ic. usb0_id, usba_id input connect to the otg power ic. usb0_vbusen usba_vbusen output usb vbus power enable pins usb0_ovrcura/ usb0_ovrcurb, usba_ovrcura/ usba_ovrcurb input usb overcurrent pins usb0_vbus, usba_vbus input usb cable connection/disc onnection detection input pins can module crx0, crx1-ds, crx2 input input pins ctx0 to ctx2 output output pins serial peripheral interface rspcka-a/rspcka-b i/o clock input/output pin mosia-a/mosia-b i/o inputs or outputs data output from the master misoa-a/misoa-b i/o inputs or outputs data output from the slave ssla0-a/ssla0-b i/o input or output pin for slave selection ssla1-a/ssla1-b to ssla3- a/ssla3-b output output pin for slave selection quad serial peripheral interface qspclk-a/-b output qspi clock output pin qssl-a/-b output qspi slave output pin qmo-a/-b, qio0-a/-b i/o master transmit data/data 0 qmi-a/-b, qio1-a/-b i/o master input data/data 1 qio2-a/-b, qio3-a/-b i/o data 2, data 3 serial sound interface ssisck0, ssi sck1 i/o ssi serial bit clock pins ssiws0, ssiws1 i/o word select pins ssitxd0, ssitxd1 output serial data output pins ssirxd0, ssirxd1 input serial data input pins ssidata0, ssidata1 i/o serial data input/output pins audio_mclk input master clock pin for audio table 1.4 pin functions (6/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 24 of 230 jul 31, 2014 mmc host interface mmc_clk-a/ mmc_clk-b output mmc clock pin mmc_cmd-a/ mmc_cmd-b i/o command/response pin mmc_d7-a/mmc_d7-b to mmc_d0-a/mmc_d0-b i/o transmit data/receive data mmc_cd-a/mmc_cd-b input card detection pin mmc_res#-a/mmc_res#-b output mmc reset output pin sd host interface sdhi_clk-a/sdhi_clk-b output sd clock output pin sdhi_cmd-a/sdhi_cmd-b i/o sd command output, response input signal pin sdhi_d3-a/sdhi_d3-b to sdhi_d0-a/sdhi_d0-b i/o sd data bus pins sdhi_cd-a/sdhi_cd-b input sd card detection pin sdhi_wp-a/sdhi_wp-b input sd write-protect signal parallel data capture unit pix clk input image transfer clock pin vsync input vertical synchronization signal pin hsync input horizontal synchronization signal pin pixd0 to pixd7 input 8-bit image data pins pcko output output pin for dot clock realtime clock rtcout output output pin for 1-hz/64-hz clock rtcic0 to rtcic2 input time capture event input pins 12-bit a/d converter an000 to an007, an100 to an120 input input pins for the analog signals to be processed by the a/d converter adtrg0#, adtrg1# input input pins for the ex ternal trigger signals that start the a/d conversion anex0 output extended analog output pin anex1 input extended analog input pin 12-bit d/a converter da0, da1 output output pins fo r the analog signals to be processed by the d/a converter analog power supply avcc0 input analog voltage suppl y pin for the 12-bit a/d converter (unit 0). connect this pin to a branch from the vcc power supply. avss0 input analog ground pin for the 12-bit a/d converter (unit 0). connect this pin to a branch from the vss ground power supply. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter (unit 0). connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 input analog reference ground pin for the 12-bit a/d converter (unit 0). connect this pin to vss if the 12-bit a/d converter is not to be used. avcc1 input analog voltage supply and reference voltage supply pin for the 12-bit a/d converter (unit 1) and d/a converter. this pin also supplies the analog voltage to the temperature sensor. connect this pin to a branch from the vcc power supply. avss1 input analog voltage supply and reference voltage supply pin for the 12-bit a/d converter (unit 1) and d/a converter. this pin also supplies the analog ground voltage to the temperature sensor. connect this pin to a branch from the vss ground power supply. table 1.4 pin functions (7/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 25 of 230 jul 31, 2014 note: note the following regarding pin names. for details, see secti on 1.5, pin assignments. ? we recommend using pins that have a letter (?-a?, ?-b?, etc.) to indicate group membership appended to their names as groups. for the rspi, qspi, sdhi, and mmc interfaces, the ac portion of the electrical characterist ics is measured for each group. ? pins that have "-ds" appended to their names can be us ed as triggers for release from deep software standby. ? riic pin functions that have [fm+] appende d to their names support fast-mode plus. i/o ports p00 to p03, p05, p07 i/o 6-bit input/output pins p10 to p17 i/o 8-bit input/output pins p20 to p27 i/o 8-bit input/output pins p30 to p37 i/o 8-bit input/output pins (p35: input pin) p40 to p47 i/o 8-bit input/output pins p50 to p56 i/o 7-bit input/output pins (176-pin devices hav e only p50 to p53) p60 to p67 i/o 8-bit input/output pins p70 to p77 i/o 8-bit input/output pins p80 to p83, p86, p87 i/o 6-bit input/output pins p90 to p97 i/o 8-bit input/output pins pa0 to pa7 i/o 8-bit input/output pins pb0 to pb7 i/o 8-bit input/output pins pc0 to pc7 i/o 8-bit input/output pins pd0 to pd7 i/o 8-bit input/output pins pe0 to pe7 i/o 8-bit input/output pins pf0 to pf5 i/o 6-bit input/output pins pg0 to pg7 i/o 8-bit input/output pins pj3, pj5 i/o 2-bit input/output pins table 1.4 pin functions (8/8) classifications pin name i/o description
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 26 of 230 jul 31, 2014 1.5 pin assignments figure 1.3 to figure 1.9 show the pin assignments. table 1.5 to table 1.10 show the lists of pins and pin functions. figure 1.3 pin assignment (177-pin tflga) abcdefghjklmnpr 15 pe2 pe3 p70 p65 p67 vss vcc pg7 pa6 pb0 p72 pb4 vss vcc pc1 15 14 pe1 pe0 vss pe7 pg3 pa0 pa1 pa2 pa7 vcc pb1 pb5 p73 p75 p74 14 13 p63 p64 pe4 vcc pg2 pg4 pg6 pa3 vss p71 pb3 pb7 pc0 pc2 p76 13 12 p60 vss p62 pe5 pe6 p66 pg5 pa4 pa5 pb2 pb6 p77 pc3 pc4 p80 12 11 pd6 pg1 vcc p61 rx64m group ptlg0177ka-a (177-pin tflga) (upper perspective view) p81 p82 pc6 vcc 11 10 p97 pd4 pg0 pd7 pc5 pc7 p83 vss 10 9 vcc p96 pd3 pd5 p50 p51 p52 p53 9 8p94 pd1 pd2 vss vcc_ usba vss1_ usba p10 p11 8 7 vss p92 pd0 p95 usba_ rref vss2_ usba usba_ dm usba_ dp 7 6vcc p91 p90 p93 avcc_ usba vss_ usb avss_ usba pvss_ usba 6 5 p46 p47 p45 p44 nc vcc_ usb p12 usb0_ dp usb0_ dm 5 4 p42 p41 p43 p00 vss bscanp pf4 p35 pf3 pf1 p25 p86 p15 p14 p13 4 3 vrefl0 p40 vrefh0 p03 pf5 pj3 md/ fined res# p34 pf2 pf0 p24 p22 p87 p16 3 2 avcc0 p07 avcc1 p02 emle vcl xcout vss vcc p32 p30 p26 p23 p17 p20 2 1 avss0 p05 avss1 p01 pj5 vbatt xcin xtal extal p33 p31 p27 vcc vss p21 1 abcdefghjklmnpr note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.5, list of pin and pin functions (177-pin tflga, 176-pin lfbga).
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 27 of 230 jul 31, 2014 figure 1.4 pin assignment (176-pin lfbga) abcdefghjklmnpr 15 pe2 pe3 p70 p65 p67 vss vcc pg7 pa6 pb0 p72 pb4 vss vcc pc1 15 14 pe1 pe0 vss pe7 pg3 pa0 pa1 pa2 pa7 vcc pb1 pb5 p73 p75 p74 14 13 p63 p64 pe4 vcc pg2 pg4 pg6 pa3 vss p71 pb3 pb7 pc0 pc2 p76 13 12 p60 vss p62 pe5 pe6 p66 pg5 pa4 pa5 pb2 pb6 p77 pc3 pc4 p80 12 11 pd6 pg1 vcc p61 rx64m group plbg0176ga-a (176-pin lfbga) (upper perspective view) p81 p82 pc6 vcc 11 10 p97 pd4 pg0 pd7 pc5 pc7 p83 vss 10 9 vcc p96 pd3 pd5 p50 p51 p52 p53 9 8p94 pd1 pd2 vss vcc_ usba vss1_ usba p10 p11 8 7 vss p92 pd0 p95 usba_ rref vss2_ usba usba_ dm usba_ dp 7 6vcc p91 p90 p93 avcc_ usba vss_ usb avss_ usba pvss_ usba 6 5 p46 p47 p45 p44 vcc_ usb p12 usb0_ dp usb0_ dm 5 4 p42 p41 p43 p00 vss bscanp pf4 p35 pf3 pf1 p25 p86 p15 p14 p13 4 3 vrefl0 p40 vrefh0 p03 pf5 pj3 md/ fined res# p34 pf2 pf0 p24 p22 p87 p16 3 2 avcc0 p07 avcc1 p02 emle vcl xcout vss vcc p32 p30 p26 p23 p17 p20 2 1 avss0 p05 avss1 p01 pj5 vbatt xcin xtal extal p33 p31 p27 vcc vss p21 1 abcdefghjklmnpr note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.5, list of pin and pin functions (177-pin tflga, 176-pin lfbga).
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 28 of 230 jul 31, 2014 figure 1.5 pin assignment (176-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pe0 p64 p63 p62 p61 vss p60 vcc pd7 pg1 pd6 pg0 pd4 p97 pd3 vss p96 vcc pd2 p95 pd1 p94 pd0 p93 p91 p90 p47 p45 p43 p41 p40 p07 pe1 pd5 avcc0 p20 pe3 pe5 vss p70 vcc pe6 pe7 p65 pg2 p66 pg3 p67 pg4 vss pg5 vcc pa1 pg6 pa2 pg7 pa3 pa4 pa5 pa6 pa7 pb0 vcc pb1 pb2 pb4 pb6 p73 pc1 pe4 pa0 vcc avss0 avcc1 p03 avss1 p02 p01 p00 pf5 emle pj5 vss pj3 vcl nc pf4 md/fined xcin xcout res# p37/xtal vss vcc p34 pf2 p30 pf0 p26 vcc vss p23 p21 p36/extal p05 vbatt p32 pe2 p35 p33 pf3 p31 pf1 p27 p25 p24 p22 p17 p87 p16 p86 p15 p14 p13 p12 vcc_usb usb0_dm usb0_dp vss_usb avcc_usba usba_rref avss_usba pvss_usba vss2_usba usba_dp vss1_usba p83 pc7 pc6 pc5 p82 p81 p80 pc4 pc3 p77 usba_dm vcc_usba p11 p10 p53 p52 p51 p50 vss vcc p76 pc2 p75 p74 vss p71 p72 pb3 pb5 pb7 pc0 vss p92 vss vcc p46 p44 p42 vrefh0 vrefl0 note: this figure indicates the power supply pi ns and i/o port pins. for the pin configur ation, see table 1.6, list of pin and p in functions (176-pin lqfp). the 16th pin nc must be connected to vss via a resistor. rx64m group plqp0176kb-a (176-pin lqfp) (top view)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 29 of 230 jul 31, 2014 figure 1.6 pin assignment (145-pin tflga) abcdefghjklmn 13 pe3 pe4 vss pe6 p67 pa2 pa4 pa7 pb1 pb5 vss vcc p74 13 12 pe1 pe2 p70 pe5 p65 pa1 vcc pb0 pb2 pb6 p73 pc1 p75 12 11 p62 p61 pe0 vcc p66 vss pa6 p71 pb4 pb7 pc2 pc0 pc3 11 10 vss vcc p63 pe7 pa0 pa3 pa5 p72 pb3 p76 pc4 p77 p82 10 9 pd6 pd4 pd7 p64 rx64m group ptlg0145ka-a (145-pin tflga) (upper perspective view) p80 pc5 p81 pc7 9 8 pd2 pd0 pd3 p60 vcc p83 pc6 vss 8 7 p92 p91 pd1 pd5 p51 p52 p50 p55 7 6 p90 p47 vss p93 p53 p56 vss_ usb usb0_ dp 6 5 p45 p43 p46 vcc p44 p54 p13 vcc_ usb usb0_ dm 5 4 p42 vrefl0 p41 p01 emle vbatt bscanp p35 p30 p15 p24 p12 p14 4 3 p40 p05 vrefh0 p03 pj5 pj3 md/ fined vss p32 p31 p16 p86 p87 3 2 p07 avcc0 p02 pf5 vcl xcout res# vcc p33 p26 p23 p17 p20 2 1 avss0 avcc1 avss1 p00 vss xcin xtal extal p34 p27 p25 p22 p21 1 abcdefghjklmn note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.7, list of pin and pin functions (145-pin tflga).
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 30 of 230 jul 31, 2014 figure 1.7 pin assignment (144-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0 p64 p63 p62 p61 vss p60 vcc pd7 pd6 pd5 pd4 pd2 pd1 pd0 p93 p92 p91 vss p90 vcc p47 p46 p45 p44 p43 p42 p41 vrefl0 p40 vrefh0 p07 pe1 pd3 avcc0 p74 pc2 p76 p77 pc3 pc4 p80 p81 p82 pc5 pc6 pc7 vcc vss p50 p51 p52 p53 p54 p55 p56 vss_usb usb0_dp usb0_dm vcc_usb p12 p13 p14 p15 p86 p16 p87 p20 p75 p83 p17 pe3 pe5 vss p70 vcc pe6 pe7 p65 p66 p67 pa0 pa1 pa2 vss pa4 vcc pa5 pa6 pa7 pb0 p71 p72 pb1 pb2 pb3 pb4 pb5 pb6 pb7 p73 vss pc0 pc1 pe4 pa3 vcc avss0 avcc1 p03 avss1 p02 p01 p00 pf5 emle pj5 vss pj3 vcl md/fined xcin xcout res# p37/xtal vss p36/extal vcc p35 p34 p32 p31 p30 p27 p26 p25 p24 p23 p21 p05 vbatt p22 p33 pe2 note: this figure indicates the power supply pi ns and i/o port pins. for the pin configurat ion, see table 1.8, list of pin and p in functions (144-pin lqfp). rx64m group plqp0144ka-a (144-pin lqfp) (top view)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 31 of 230 jul 31, 2014 figure 1.8 pin assignment (100-pin tflga) rx64m group ptlg0100ja-a (100-pin tflga) (upper perspective view) abcdefghjk 10 pe2 pe3 pe4 pa0 pa3 vss vcc pb7 pc1 pc2 10 9 pe1 pd7 pe5 pa1 pa5 pa7 pb1 pb6 pc0 pc3 9 8 pe0 pd6 pd5 pe7 pa4 pb0 pb4 pc6 pc4 pc5 8 7 pd4 pd3 pd2 pe6 pa6 pb2 pb5 pc7 p50 p51 7 6 pd0 pd1 p47 p46 pa2 pb3 p52 p54 vcc_ usb usb0_ dp 6 5 p43 p44 p42 p45 p41 p12 p53 p55 vss_ usb usb0_ dm 5 4 vrefl0 p40 vrefh0 vbatt p34 p32 p27 p15 p13 p14 4 3 p07 avcc0 pj3 md/ fined res# p35 p30 p16 p17 p20 3 2 avcc1 avss0 avss1 xcout vss vcc p31 p25 p21 p22 2 1 p05 emle vcl xcin xtal extal p33 p26 p24 p23 1 abcdefghjk note: this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see table 1.9, list of pin and pin functions (100-pin tflga).
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 32 of 230 jul 31, 2014 figure 1.9 pin assignment (100-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 vss_usb usb0_dp vcc_usb p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 usb0_dm pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 avcc1 avss1 pj3 vcl vbatt md/fined xcin xcout res# p37/xtal vss p36/extal p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 emle vcc pe2 p05 p24 note: this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.10, list of pin a nd pin functions (100-pin lqfp). rx64m group plqp0100kb-a (100-pin lqfp) (top view)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 33 of 230 jul 31, 2014 table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (1/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 avss0 a2 avcc0 a3 vrefl0 a4 p42 irq10- ds an002 a5 p46 irq14- ds an006 a6 vcc a7 vss a8 p94 a20/d20 et1_erxd0/ rmii1_rxd0 a9 vcc a10 p97 a23/d23 et1_erxd3 a11 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 a12 p60 cs0# et1_tx_en/ rmii1_txd_en a13 p63 cs3#/cas# a14 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a15 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/ rxdx12 mmc_d6-b irq7-ds an100 b1 p05 irq13 da1 b2 p07 irq15 adtrg0# b3 p40 irq8-ds an000 b4 p41 irq9-ds an001 b5 p47 irq15- ds an007 b6 p91 a17/d17 et1_col/sck7 an115 b7 p92 a18/d18 poe4# et1_crs/ rmii1_crs_dv/ rxd7/smiso7/sscl7 an116 b8 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 b9 p96 a22/d22 et1_erxd2 b10 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 b11 pg1 d25 et1_rx_er/ rmii1_rx_er b12 vss b13 p64 cs4#/we# b14 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 b15 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/ et0_erxd3 mmc_d7-b an101 c1 avss1 c2 avcc1 c3 vrefh0
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 34 of 230 jul 31, 2014 c4 p43 irq11-ds an003 c5 p45 irq13- ds an005 c6 p90 a16/d16 et1_rx_dv/ txd7/smosi7/ssda7 an114 c7 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 c8 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2_b irq2 an110 c9 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 c10 pg0 d24 et1_rx_clk/ ref50ck1 c11 vcc c12 p62 cs2#/ras# c13 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 c14 vss c15 p70 sdclk d1 p01 tmci0 rxd6/smiso6/ sscl6 irq9 an119 d2 p02 tmci1 sck6 irq10 an120 d3 p03 irq11 da0 d4 p00 tmri0 txd6/smosi6/ ssda6 irq8 an118 d5 p44 irq12- ds an004 d6 p93 a19/d19 poe0# et1_linksta/cts7#/ rts7#/ss7# an117 d7 p95 a21/d21 et1_erxd1/ rmii1_rxd1 d8 vss d9 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 d10 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 d11 p61 cs1#/sdcs# d12 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 d13 vcc d14 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d15 p65 cs5#/cke e1 pj5 poe8# cts2#/rts2#/ss2# e2 emle e3 pf5 irq4 e4 vss e5* 1 e12 pe6 d14[a14/d14] mtioc6c/ gtioc3b-e/tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 e13 trdata0 pg2 d26 et1_tx_clk table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (2/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 35 of 230 jul 31, 2014 e14 trdata1 pg3 d27 et1_etxd0/ rmii1_txd0 e15 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 f1 vbatt f2 vcl f3 pj3 edack1 mtioc3c et0_exout/ cts6#/rts6#/ cts0#/rts0#/ ss6#/ss0# f4 bscanp f12 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 f13 trsync pg4 d28 et1_etxd1/ rmii1_txd1 f14 pa0 a0/bc0#/ dqm2 mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en f15 vss g1 xcin g2 xcout g3 md/fined g4 trst# pf4 g12 trclk pg5 d29 et1_etxd2 g13 trdata2 pg6 d30 et1_etxd3 g14 pa1 a1/dqm3 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 g15 vcc h1 xtal p37 h2 vss h3 res# h4 upsel p35 nmi h12 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds h13 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/ et0_mdio irq6-ds h14 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b h15 trdata3 pg7 d31 et1_tx_er j1 extal p36 j2 vcc j3 p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 j4 tms pf3 j12 pa5 a5 mtioc6b/ gtioc0a-c/tiocb1/ po21 rspcka-b/ et0_linksta j13 vss j14 pa7 a7 tiocb2/po23 misoa-b/ et0_wol table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (3/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 36 of 230 jul 31, 2014 j15 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout k1 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/ smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds k2 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/ smosi6/smosi0/ ssda6/ssda0/ ctx0/ usb0_vbusen vsync irq2-ds k3 tdi pf2 rxd1/smiso1/ sscl1 k4 tck pf1 sck1 k12 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 k13 p71 a18/cs1# et0_mdio k14 vcc k15 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 l1 p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ ss1#/et1_mdc irq1-ds l2 p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/ sscl1/ et1_mdio irq0-ds l3 tdo pf0 txd1/smosi1/ ssda1 l4 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ ssidata1 hsync adtrg0# l12 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 l13 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er l14 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds l15 p72 a19/cs2# et0_mdc m1 p27 cs7# mtioc2b/tmci3/po7 sck1/et1_wol m2 p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/ rts3#/smosi1/ ss3#/ssda1/ et1_exout m3 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk m4 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 m5 vcc_usb p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 m6 avcc_ usba table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (4/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 37 of 230 jul 31, 2014 m7 usba_ rref p11 mtic5v/tmci3 sck2/usba_vbus/ usba_vbusen irq1 m8 vcc_ usba p10 ale mtic5w/tmri3 usba_ovrcura irq0 m9 p50 wr0#/wr# txd2/smosi2/ssda2 m10 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a m11 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a m12 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a m13 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv m14 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 m15 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en n1 vcc n2 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/ rts0#/smosi3/ ss0#/ssda3/ ssisck0 pixd7 n3 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ usba_ovrcurb/ audio_mclk pixd6 n4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/ smiso1/sscl1/ crx1-ds/ usba_vbusen/ ssiws1 pixd0 irq5 n5 p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 n6 vss_usb n7 vss2_ usba n8 vss1_ usba n9 p51 wr1#/bc1#/ wait# sck2 n10 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 n11 p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a n12 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/ et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a n13 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 n14 p73 cs3# po16 et0_wol n15 vss p1 vss table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (5/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 38 of 230 jul 31, 2014 p2 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/ smosi3/ssda3/ sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# p3 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 p4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ ss1#/ctx1/ usb0_ovrcura irq4 p5 usb0_dp p6 avss_ usba p7 usba_dm p8 p10 ale mtic5w/tmri3 usba_ovrcura irq0 p9 p52 rd# rxd2/smiso2/ sscl2 p10 p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 p11 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 p12 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a p13 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv/ mmc_cd-a/ sdhi_d3-a p14 p75 cs5# po20 sck11/rts11/ et0_erxd0/ rmii0_rxd0/ mmc_res#-a/ sdhi_d2-a p15 vcc r1 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ usba_exicen/ ssiws0 pixd5 irq9 r2 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ usba_id/ ssirxd0 pixd4 irq8 r3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/ smosi1/smiso3/ ssda1/sscl3/ scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# r4 p13 wr2#/bc2# mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/ sda0[fm+] irq3 adtrg1# r5 usb0_dm r6 pvss_ usba r7 usba_dp r8 p11 mtic5v/tmci3 sck2/ usba_vbus/ usba_vbusen r9 p53* 2 bclk r10 vss table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (6/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 39 of 230 jul 31, 2014 note 1. the 176-pin lfbga does not include the e5 pin. note 2. the bclk function is multiplexed with the i/o port functi on for pin p53, so the port function is not available if the ex ternal bus is enabled. r11 vcc r12 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a r13 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a r14 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 r15 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 table 1.5 list of pin and pin function s (177-pin tflga, 176- pin lfbga) (7/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 177-pin tflga 176-pin lfbga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 40 of 230 jul 31, 2014 table 1.6 list of pin and pin functions (176-pin lqfp) (1/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avss0 2p05 irq13 da1 3 avcc1 4p03 irq11 da0 5 avss1 6 p02 tmci1 sck6 irq10 an120 7 p01 tmci0 rxd6/smiso6/ sscl6 irq9 an119 8 p00 tmri0 txd6/smosi6/ ssda6 irq8 an118 9pf5 irq4 10 emle 11 pj5 poe8# cts2#/rts2#/ss2# 12 vss 13 pj3 edack1 mtioc3c et0_exout/ cts6#/rts6#/ cts0#/rts0#/ ss6#/ss0# 14 vcl 15 vbatt 16 nc 17 trst# pf4 18 md/fined 19 xcin 20 xcout 21 res# 22 xtal p37 23 vss 24 extal p36 25 vcc 26 upsel p35 nmi 27 p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 28 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/ smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds 29 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/ smosi6/smosi0/ ssda6/ssda0/ ctx0/ usb0_vbusen vsync irq2-ds 30 tms pf3 31 tdi pf2 rxd1/smiso1/ sscl1 32 p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ ss1#/et1_mdc irq1-ds 33 p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/ sscl1/ et1_mdio irq0-ds 34 tck pf1 sck1 35 tdo pf0 txd1/smosi1/ ssda1
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 41 of 230 jul 31, 2014 36 p27 cs7# mtioc2b/tmci3/po7 sck1/et1_wol 37 p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/ rts3#/smosi1/ ss3#/ssda1/ et1_exout 38 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ ssidata1 hsync adtrg0# 39 vcc 40 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk 41 vss 42 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/ rts0#/smosi3/ ss0#/ssda3/ ssisck0 pixd7 43 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ usba_ovrcurb/ audio_mclk pixd6 44 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ usba_exicen/ ssiws0 pixd5 irq9 45 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ usba_id/ ssirxd0 pixd4 irq8 46 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/ smosi3/ssda3/ sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# 47 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 48 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/ smosi1/smiso3/ ssda1/sscl3/ scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 49 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 50 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/ smiso1/sscl1/ crx1-ds/ usba_vbusen/ ssiws1 pixd0 irq5 51 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ ss1#/ctx1/ usb0_ovrcura irq4 52 p13 wr2#/bc2# mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/ sda0[fm+] irq3 adtrg1# 53 p12 wr3#/bc3# mtic5u/tmci1 rxd2/smiso2/ sscl2/ scl0[fm+] irq2 54 vcc_usb 55 usb0_dm 56 usb0_dp table 1.6 list of pin and pin functions (176-pin lqfp) (2/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 42 of 230 jul 31, 2014 57 vss_usb 58 avcc_ usba 59 usba_ rref 60 avss_ usba 61 pvss_ usba 62 vss2_ usba 63 usba_dm 64 usba_dp 65 vss1_ usba 66 vcc_ usba 67 p11 mtic5v/tmci3 sck2/usba_vbus/ usba_vbusen irq1 68 p10 ale mtic5w/tmri3 usba_ovrcura irq0 69 p53* 1 bclk 70 p52 rd# rxd2/smiso2/sscl2 71 p51 wr1#/bc1#/ wait# sck2 72 p50 wr0#/wr# txd2/smosi2/ssda2 73 vss 74 p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 75 vcc 76 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 77 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 78 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a 79 p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a 80 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a 81 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a 82 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a 83 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/ et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a 84 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a table 1.6 list of pin and pin functions (176-pin lqfp) (3/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 43 of 230 jul 31, 2014 85 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a 86 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a 87 p75 cs5# po20 sck11/rts11#/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a 88 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 89 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 90 vcc 91 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 92 vss 93 p73 cs3# po16 et0_wol 94 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 95 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 96 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 97 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en 98 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er 99 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 100 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 101 p72 a19/cs2# et0_mdc 102 p71 a18/cs1# et0_mdio 103 vcc 104 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 105 vss 106 pa7 a7 tiocb2/po23 misoa-b/ et0_wol 107 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 108 pa5 a5 mtioc6b/ gtioc0a-c/tiocb1/ po21 rspcka-b/ et0_linksta 109 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds 110 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/ et0_mdio irq6-ds table 1.6 list of pin and pin functions (176-pin lqfp) (4/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 44 of 230 jul 31, 2014 111 trdata3 pg7 d31 et1_tx_er 112 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b 113 trdata2 pg6 d30 et1_etxd3 114 pa1 a1/dqm3 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 115 vcc 116 trclk pg5 d29 et1_etxd2 117 vss 118 pa0 a0/bc0#/ dqm2 mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en 119 trsync pg4 d28 et1_etxd1/ rmii1_txd1 120 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 121 trdata1 pg3 d27 et1_etxd0/ rmii1_txd0 122 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 123 trdata0 pg2 d26 et1_tx_clk 124 p65 cs5#/cke 125 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 126 pe6 d14[a14/d14] mtioc6c/ gtioc3b-e/tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 127 vcc 128 p70 sdclk 129 vss 130 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 131 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 132 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/ et0_erxd3 mmc_d7-b an101 133 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/ rxdx12 mmc_d6-b irq7-ds an100 134 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 135 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 136 p64 cs4#/we# 137 p63 cs3#/cas# 138 p62 cs2#/ras# 139 p61 cs1#/sdcs# 140 vss 141 p60 cs0# et1_tx_en/ rmii1_txd_en 142 vcc table 1.6 list of pin and pin functions (176-pin lqfp) (5/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 45 of 230 jul 31, 2014 143 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 144 pg1 d25 et1_rx_er/ rmii1_rx_er 145 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 146 pg0 d24 et1_rx_clk/ ref50ck1 147 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 148 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 149 p97 a23/d23 et1_erxd3 150 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 151 vss 152 p96 a22/d22 et1_erxd2 153 vcc 154 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2_b irq2 an110 155 p95 a21/d21 et1_erxd1/ rmii1_rxd1 156 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 157 p94 a20/d20 et1_erxd0/ rmii1_rxd0 158 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 159 p93 a19/d19 poe0# et1_linksta/cts7#/ rts7#/ss7# an117 160 p92 a18/d18 poe4# et1_crs/ rmii1_crs_dv/ rxd7/smiso7/sscl7 an116 161 p91 a17/d17 et1_col/sck7 an115 162 vss 163 p90 a16/d16 et1_rx_dv/ txd7/smosi7/ssda7 an114 164 vcc 165 p47 irq15- ds an007 166 p46 irq14- ds an006 167 p45 irq13- ds an005 168 p44 irq12- ds an004 169 p43 irq11-ds an003 170 p42 irq10- ds an002 171 p41 irq9-ds an001 172 vrefl0 table 1.6 list of pin and pin functions (176-pin lqfp) (6/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 46 of 230 jul 31, 2014 note 1. the bclk function is multiplexed with the i/o port functi on for pin p53, so the port function is not available if the ex ternal bus is enabled. 173 p40 irq8-ds an000 174 vrefh0 175 avcc0 176 p07 irq15 adtrg0# table 1.6 list of pin and pin functions (176-pin lqfp) (7/7) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 176-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 47 of 230 jul 31, 2014 table 1.7 list of pin and pin functions (145-pin tflga) (1/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 avss0 a2 p07 irq15 adtrg0# a3 p40 irq8-ds an000 a4 p42 irq10- ds an002 a5 p45 irq13- ds an005 a6 p90 a16 txd7/smosi7/ssda7 an114 a7 p92 a18 poe4# rxd7/smiso7/sscl7 an116 a8 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 a9 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 a10 vss a11 p62 cs2#/ras# a12 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a13 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3/ mmc_d7-b an101 b1 avcc1 b2 avcc0 b3 p05 irq13 da1 b4 vrefl0 b5 p43 irq11-ds an003 b6 p47 irq15- ds an007 b7 p91 a17 sck7 an115 b8 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 b9 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 b10 vcc b11 p61 cs1#/sdcs# b12 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12/ mmc_d6-b irq7-ds an100 b13 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 c1 avss1 c2 p02 tmci1 sck6 irq10 an120 c3 vrefh0 c4 p41 irq9-ds an001 c5 p46 irq14- ds an006 c6 vss c7 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 c8 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 48 of 230 jul 31, 2014 c9 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 c10 p63 cs3#/cas# c11 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 c12 p70 sdclk c13 vss d1 p00 tmri0 txd6/smosi6/ssda6 irq8 an118 d2 pf5 irq4 d3 p03 irq11 da0 d4 p01 tmci0 rxd6/smiso6/sscl6 irq9 an119 d5 vcc d6 p93 a19 poe0# cts7#/rts7#/ss7# an117 d7 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 d8 p60 cs0# d9 p64 cs4#/we# d10 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d11 vcc d12 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 d13 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 e1 vss e2 vcl e3 pj5 poe8# cts2#/rts2#/ss2# e4 emle e5 p44 irq12- ds an004 e10 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-a/ et0_tx_en/ rmii0_txd_en e11 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 e12 p65 cs5#/cke e13 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 f1 xcin f2 xcout f3 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# f4 vbatt f10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds f11 vss f12 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-a/ et0_wol irq11 table 1.7 list of pin and pin functions (145-pin tflga) (2/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 49 of 230 jul 31, 2014 f13 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-a g1 xtal p37 g2 res g3 md/fined g4 bscanp g10 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta g11 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout g12 vcc g13 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-a/ et0_mdc irq5-ds h1 extal p36 h2 vcc h3 vss h4 upsel p35 nmi h10 p72 a19/cs2# et0_mdc h11 p71 a18/cs1# et0_mdio h12 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 h13 pa7 a7 tiocb2/po23 misoa-b/et0_wol j1 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 j2 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds j3 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen vsync irq2-ds j4 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds j10 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er j11 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en j12 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 j13 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds k1 tck p27 cs7# mtioc2 b/tmci3/po7 sck1 k2 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 k3 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds k4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 pixd0 irq5 table 1.7 list of pin and pin functions (145-pin tflga) (3/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 50 of 230 jul 31, 2014 k5 trdata2 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta k6 p53 bclk k7 p51 wr1#/bc1#/ wait# sck2 k8 vcc k9 trdata0 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a k10 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a k11 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv k12 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 k13 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 l1 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 hsync adtrg0# l2 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 pixd7 l3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# l4 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk l5 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# l6 p56 edack1 mtioc3c/tioca1 l7 p52 rd# rxd2/smiso2/sscl2 l8 trclk p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 l9 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a l10 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a l11 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a l12 p73 cs3# po16 et0_wol l13 vss m1 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk pixd6 m2 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# m3 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 table 1.7 list of pin and pin functions (145-pin tflga) (4/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 51 of 230 jul 31, 2014 m4 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 m5 vcc_usb m6 vss_usb m7 p50 wr0#/wr# txd2/smosi2/ssda2 m8 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 m9 trdata1 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a m10 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a m11 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 m12 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 m13 vcc n1 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 pixd5 irq9 n2 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 pixd4 irq8 n3 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 n4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 n5 usb0_dm n6 usb0_dp n7 trdata3 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 n8 vss n9 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 n10 trsync p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a n11 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a n12 p75 cs5# po20 sck11/rts11#/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a n13 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 table 1.7 list of pin and pin functions (145-pin tflga) (5/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 145-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 52 of 230 jul 31, 2014 table 1.8 list of pin and pin functions (144-pin lqfp) (1/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avss0 2p05 irq13 da1 3 avcc1 4p03 irq11 da0 5 avss1 6 p02 tmci1 sck6 irq10 an120 7 p01 tmci0 rxd6/smiso6/sscl6 irq9 an119 8 p00 tmri0 txd6/smosi6/ssda6 irq8 an118 9pf5 irq4 10 emle 11 pj5 poe8# 12 vss 13 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# 14 vcl 15 vbatt 16 md/fined 17 xcin 18 xcout 19 res 20 xtal p37 21 vss 22 extal p36 23 vcc 24 p35 nmi 25 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 26 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 pcko irq3-ds 27 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen vsync irq2-ds 28 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds 29 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds 30 tck p27 cs7# mtioc2b/tmci3/po7 sck1 31 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 32 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 hsync adtrg0# 33 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 pixclk 34 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 pixd7 35 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk pixd6
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 53 of 230 jul 31, 2014 36 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 pixd5 irq9 37 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 pixd4 irq8 38 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 pixd3 irq7 adtrg1# 39 p87 mtioc4c/ gtioc1b-b/tioca2 txd10 pixd2 40 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 41 p86 mtioc4d/ gtioc2b-b/tioca0 rxd10 pixd1 42 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 pixd0 irq5 43 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 44 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# 45 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 46 vcc_usb 47 usb0_dm 48 usb0_dp 49 vss_usb 50 p56 edack1 mtioc3c/tioca1 51 trdata3 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 52 trdata2 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta 53 p53 bclk 54 p52 rd# rxd2/smiso2/sscl2 55 p51 wr1#/bc1#/ wait# sck2 56 p50 wr0#/wr# txd2/smosi2/ssda2 57 vss 58 trclk p83 edack1 mtioc4c/ gtioc0a-d cts10#/et0_crs/ rmii0_crs_dv/ sck10 59 vcc 60 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col mmc_d7-a irq14 61 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 mmc_d6-a irq13 62 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 mmc_d5-a table 1.8 list of pin and pin functions (144-pin lqfp) (2/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 54 of 230 jul 31, 2014 63 trsync p82 edreq1 mtioc4a/ gtioc2a-d/po28 txd10/et0_etxd1/ rmii0_txd1 mmc_d4-a 64 trdata1 p81 edack0 mtioc3d/ gtioc0b-d/po27 rxd10/et0_etxd0/ rmii0_txd0 mmc_d3-a/ sdhi_cd-a/ qio3-a 65 trdata0 p80 edreq0 mtioc3b/po26 sck10/rts10#/ et0_tx_en/ rmii0_txd_en mmc_d2-a/ sdhi_wp-a/ qio2-a 66 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk/ mmc_d1-a/ sdhi_d1-a/ qio1-a/qmi-a 67 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er mmc_d0-a/ sdhi_d0-a/ qio0-a/ qmo-a 68 p77 cs7# po23 txd11/et0_rx_er/ rmii0_rx_er mmc_clk-a/ sdhi_clk-a/ qspclk-a 69 p76 cs6# po22 rxd11/et0_rx_clk/ ref50ck0 mmc_cmd-a/ sdhi_cmd-a/ qssl-a 70 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv mmc_cd-a/ sdhi_d3-a 71 p75 cs5# po20 sck11/rts11/ et0_erxd0/ rmii0_rxd0 mmc_res#-a/ sdhi_d2-a 72 p74 a20/cs4# po19 cts11#/et0_erxd1/ rmii0_rxd1 73 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 74 vcc 75 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 76 vss 77 p73 cs3# po16 et0_wol 78 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 79 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 80 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 81 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en 82 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck4/sck6/ et0_rx_er/ rmii0_rx_er 83 pb2 a10 tiocc3/tclkc/ po26 cts4#/rts4#/cts6#/ rts6#/ss4#/ss6#/ et0_rx_clk/ ref50ck0 84 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd4/txd6/smosi4/ smosi6/ssda4/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 85 p72 a19/cs2# et0_mdc 86 p71 a18/cs1# et0_mdio table 1.8 list of pin and pin functions (144-pin lqfp) (3/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 55 of 230 jul 31, 2014 87 pb0 a8 mtic5w/tioca3/ po24 rxd4/rxd6/smiso4/ smiso6/sscl4/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 88 pa7 a7 tiocb2/po23 misoa-b/et0_wol 89 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 90 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta 91 vcc 92 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-a/ et0_mdc irq5-ds 93 vss 94 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds 95 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-a 96 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-a/ et0_wol irq11 97 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-a/ et0_tx_en/ rmii0_txd_en 98 p67 cs7#/dqm1 mtioc7c/ gtioc1b-c crx2 irq15 99 p66 cs6#/dqm0 mtioc7d/ gtioc2b-c ctx2 100 p65 cs5#/cke 101 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 102 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 103 vcc 104 p70 sdclk 105 vss 106 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 107 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 108 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3/ mmc_d7-b an101 109 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12/ mmc_d6-b irq7-ds an100 110 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 111 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 112 p64 cs4#/we# 113 p63 cs3#/cas# 114 p62 cs2#/ras# 115 p61 cs1#/sdcs# 116 vss table 1.8 list of pin and pin functions (144-pin lqfp) (4/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 56 of 230 jul 31, 2014 117 p60 cs0# 118 vcc 119 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/qmi-b irq7 an107 120 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/qmo- b irq6 an106 121 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 122 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 123 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 124 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 125 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 126 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 127 p93 a19 poe0# cts7#/rts7#/ss7# an117 128 p92 a18 poe4# rxd7/smiso7/sscl7 an116 129 p91 a17 sck7 an115 130 vss 131 p90 a16 txd7/smosi7/ssda7 an114 132 vcc 133 p47 irq15- ds an007 134 p46 irq14- ds an006 135 p45 irq13- ds an005 136 p44 irq12- ds an004 137 p43 irq11-ds an003 138 p42 irq10- ds an002 139 p41 irq9-ds an001 140 vrefl0 141 p40 irq8-ds an000 142 vrefh0 143 avcc0 144 p07 irq15 adtrg0# table 1.8 list of pin and pin functions (144-pin lqfp) (5/5) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 144-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 57 of 230 jul 31, 2014 table 1.9 list of pin and pin functions (100-pin tflga) (1/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) a1 p05 irq13 da1 a2 avcc1 a3 p07 irq15 adtrg0# a4 vrefl0 a5 p43 irq11- ds an003 a6 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 a7 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 a8 pe0 d8[a8/d8] mtioc3d/gtioc2b- a sck12 mmc_d4-b anex0 a9 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 a10 pe2 d10[a10/ d10] mtioc4a/gtioc0b- a/po23/tic3 rxd12/smiso12/ sscl12/rxdx12 mmc_d6-b irq7-ds an100 b1 emle b2 avss0 b3 avcc0 b4 p40 irq8-ds an000 b5 p44 irq12- ds an004 b6 pd1 d1[a1/d1] mtioc4b/gtioc1a- e/poe0# ctx0 irq1 an109 b7 pd3 d3[a3/d3] mtioc8d/gtioc0a- e/poe8#/toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 b8 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/qmo-b irq6 an106 b9 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1/qmi-b irq7 an107 b10 pe3 d11[a11/ d11] mtioc4b/gtioc2a- a/po26/poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3 mmc_d7-b an101 c1 vcl c2 avss1 c3 pj3 edack1 mtioc3c et0_exout/cts6#/ rts6#/cts0#/rts0#/ ss6#/ss0# c4 vrefh0 c5 p42 irq10- ds an002 c6 p47 irq15- ds an007 c7 pd2 d2[a2/d2] mtioc4d/gtioc0b- e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 58 of 230 jul 31, 2014 c8 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 c9 pe5 d13[a13/ d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 c10 pe4 d12[a12/ d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 d1 xcin d2 xcout d3 md/fined d4 vbatt d5 p45 irq13- ds an005 d6 p46 irq14- ds an006 d7 pe6 d14[a14/ d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 d8 pe7 d15[a15/ d15] mtioc6a/gtioc3a- e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 d9 pa1 a1 mtioc0b/mtclkc/ mtioc7b/gtioc2a- c/tiocb0/po17 sck5/ssla2-b/ et0_wol irq11 d10 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en e1 xtal p37 e2 vss e3 res# e4 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 e5 p41 irq9-ds an001 e6 pa2 a2 mtioc7a/gtioc1a- c/po18 rxd5/smiso5/ sscl5/ssla3-b e7 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout e8 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds e9 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta e10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds f1 extal p36 f2 vcc f3 upsel p35 nmi f4 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen irq2-ds f5 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 table 1.9 list of pin and pin functions (100-pin tflga) (2/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 59 of 230 jul 31, 2014 f6 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck6/et0_rx_er/ rmii0_rx_er f7 pb2 a10 tiocc3/tclkc/ po26 cts6#/rts6#ss6#/ et0_rx_clk/ ref50ck0 f8 pb0 a8 mtic5w/tioca3/ po24 rxd6/smiso6/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 f9 pa7 a7 tiocb2/po23 misoa-a/et0_wol f10 vss g1 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 irq3-ds g2 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds g3 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds g4 tck p27 cs7# mtioc2b/tmci3/po7 sck1 g5 p53 bclk g6 p52 rd# rxd2/smiso2/sscl2 g7 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 g8 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en g9 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd6/smosi6/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds g10 vcc h1 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 h2 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 adtrg0# h3 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# h4 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 irq5 h5 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 h6 p54 ale/ edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta h7 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col irq14 h8 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 irq13 table 1.9 list of pin and pin functions (100-pin tflga) (3/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 60 of 230 jul 31, 2014 h9 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 h10 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv j1 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 j2 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 irq9 j3 p17 mtioc3a/mtioc3b/ mtioc4b/gtioc0b- b/tiocb0/tclkd/ tmo1/po15/poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 irq7 adtrg1# j4 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# j5 vss_usb j6 vcc_usb j7 p50 wr0#/wr# txd2/smosi2/ssda2 j8 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ssla0- a/et0_tx_clk j9 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 j10 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 k1 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 k2 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk k3 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 irq8 k4 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 k5 usb0_dm k6 usb0_dp k7 p51 wr1#/bc1#/ wait# sck2 k8 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 k9 pc3 a19 mtioc4d/gtioc1b- d/tclkb/po24 txd5/smosi5/ ssda5/et0_tx_er k10 pc2 a18 mtioc4b/gtioc2b- d/tclka/po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv table 1.9 list of pin and pin functions (100-pin tflga) (4/4) pin number power supply clock system control i/o port bus exdmac sdramc timer communication memory interface camera interface interrupt s12adc, r12da 100-pin tflga (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 61 of 230 jul 31, 2014 table 1.10 list of pin and pin functions (100-pin lqfp) (1/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc) 1 avcc1 2emle 3 avss1 4 pj3 edack1 mtioc3c et0_exout cts6#/rts6#/cts0#/ rts0#/ss6#/ss0# 5vcl 6vbatt 7 md/fined 8xcin 9xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 upsel p35 nmi 16 trst# p34 mtioc0a/tmci3/ po12/poe10# sck6/sck0/ et0_linksta irq4 17 p33 edreq1 mtioc0d/tiocd0/ tmri3/po11/poe4#/ poe11# rxd6/rxd0/smiso6/ smiso0/sscl6/ sscl0/crx0 irq3-ds 18 p32 mtioc0c/tiocc0/ tmo3/po10/ rtcout/rtcic2/ poe0#/poe10# txd6/txd0/smosi6/ smosi0/ssda6/ ssda0/ctx0/ usb0_vbusen irq2-ds 19 tms p31 mtioc4d/tmci2/ po9/rtcic1 cts1#/rts1#/ss1# irq1-ds 20 tdi p30 mtioc4b/tmri3/ po8/rtcic0/poe8# rxd1/smiso1/sscl1 irq0-ds 21 tck p27 cs7# mtioc2b/tmci3/po7 sck1 22 tdo p26 cs6# mtioc2a/tmo1/po6 txd1/cts3#/rts3#/ smosi1/ss3#/ssda1 23 p25 cs5#/ edack1 mtioc4c/mtclkb/ tioca4/po5 rxd3/smiso3/ sscl3/ssidata1 adtrg0# 24 p24 cs4#/ edreq1 mtioc4a/mtclka/ tiocb4/tmri1/po4 sck3/ usb0_vbusen/ ssisck1 25 p23 edack0 mtioc3d/mtclkd/ gtioc0a-b/tiocd3/ po3 txd3/cts0#/rts0#/ smosi3/ss0#/ ssda3/ssisck0 26 p22 edreq0 mtioc3b/mtclkc/ gtioc1a-b/tiocc3/ tmo0/po2 sck0/ usb0_ovrcurb/ audio_mclk 27 p21 mtioc1b/mtioc4a/ gtioc2a-b/tioca3/ tmci0/po1 rxd0/smiso0/ sscl0/ usb0_exicen/ ssiws0 irq9 28 p20 mtioc1a/tiocb3/ tmri0/po0 txd0/smosi0/ ssda0/usb0_id/ ssirxd0 irq8 29 p17 mtioc3a/mtioc3b/ mtioc4b/ gtioc0b-b/tiocb0/ tclkd/tmo1/po15/ poe8# sck1/txd3/smosi3/ ssda3/sda2-ds/ ssitxd0 irq7 adtrg1#
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 62 of 230 jul 31, 2014 30 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/ tmo2/po14/ rtcout txd1/rxd3/smosi1/ smiso3/ssda1/ sscl3/scl2-ds/ usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6 adtrg0# 31 p15 mtioc0b/mtclkb/ gtetrg-b/tiocb2/ tclkb/tmci2/po13 rxd1/sck3/smiso1/ sscl1/crx1-ds/ ssiws1 irq5 32 p14 mtioc3a/mtclka/ tiocb5/tclka/ tmri2/po15 cts1#/rts1#/ss1#/ ctx1/ usb0_ovrcura irq4 33 p13 mtioc0b/tioca5/ tmo3/po13 txd2/smosi2/ ssda2/sda0[fm+] irq3 adtrg1# 34 p12 tmci1 rxd2/smiso2/ sscl2/scl0[fm+] irq2 35 vcc_usb 36 usb0_dm 37 usb0_dp 38 vss_usb 39 p55 wait#/ edreq0 mtioc4d/tmo3 crx1/et0_exout irq10 40 p54 ale/edack0 mtioc4b/tmci1 cts2#/rts2#/ss2#/ ctx1/et0_linksta 41 p53 bclk 42 p52 rd# rxd2/smiso2/sscl2 43 p51 wr1#/bc1#/ wait# sck2 44 p50 wr0#/wr# txd2/smosi2/ssda2 45 ub pc7 a23/cs0# mtioc3a/mtclkb/ gtioc3a-d/tmo2/ toc0/po31/cacref txd8/misoa-a/ et0_col irq14 46 pc6 a22/cs1# mtioc3c/mtclka/ gtioc3b-d/tmci2/ tic0/po30 rxd8/mosia-a/ et0_etxd3 irq13 47 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/ gtioc1a-d/tmri2/ po29 sck8/rspcka-a/ rts8#/et0_etxd2 48 pc4 a20/cs3# mtioc3d/mtclkc/ gtetrg-d/tmci1/ po25/poe0# sck5/cts8#/ ssla0-a/ et0_tx_clk 49 pc3 a19 mtioc4d/ gtioc1b-d/tclkb/ po24 txd5/smosi5/ ssda5/et0_tx_er 50 pc2 a18 mtioc4b/ gtioc2b-d/tclka/ po21 rxd5/smiso5/ sscl5/ssla3-a/ et0_rx_dv 51 pc1 a17 mtioc3a/tclkd/ po18 sck5/ssla2-a/ et0_erxd2 irq12 52 pc0 a16 mtioc3c/tclkc/ po17 cts5#/rts5#/ss5#/ ssla1-a/et0_erxd3 irq14 53 pb7 a15 mtioc3b/tiocb5/ po31 txd9/et0_crs/ rmii0_crs_dv 54 pb6 a14 mtioc3d/tioca5/ po30 rxd9/et0_etxd1/ rmii0_txd1 55 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/po29/ poe4# sck9/rts9#/ et0_etxd0/ rmii0_txd0 56 pb4 a12 tioca4/po28 cts9#/et0_tx_en/ rmii0_txd_en table 1.10 list of pin and pin functions (100-pin lqfp) (2/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 63 of 230 jul 31, 2014 57 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/ tmo0/po27/poe11# sck6/et0_rx_er/ rmii0_rx_er 58 pb2 a10 tiocc3/tclkc/ po26 cts6#/rts6#ss6#/ et0_rx_clk/ ref50ck0 59 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0/po25 txd6/smosi6/ ssda6/et0_erxd0/ rmii0_rxd0 irq4-ds 60 vcc 61 pb0 a8 mtic5w/tioca3/ po24 rxd6/smiso6/ sscl6/et0_erxd1/ rmii0_rxd1 irq12 62 vss 63 pa7 a7 tiocb2/po23 misoa-a/et0_wol 64 pa6 a6 mtic5v/mtclkb/ gtetrg-c/tioca2/ tmci3/po22/poe10# cts5#/rts5#/ss5#/ mosia-b/ et0_exout 65 pa5 a5 mtioc6b/tiocb1/ gtioc0a-c/po21 rspcka-b/ et0_linksta 66 pa4 a4 mtic5u/mtclka/ tioca1/tmri0/po20 txd5/smosi5/ ssda5/ssla0-b/ et0_mdc irq5-ds 67 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb/po19 rxd5/smiso5/ sscl5/et0_mdio irq6-ds 68 pa2 a2 mtioc7a/ gtioc1a-c/po18 rxd5/smiso5/ sscl5/ssla3-b 69 pa1 a1 mtioc0b/mtclkc/ mtioc7b/ gtioc2a-c/tiocb0/ po17 sck5/ssla2-b/ et0_wol irq11 70 pa0 a0/bc0# mtioc4a/mtioc6d/ gtioc0b-c/tioca0/ cacref/po16 ssla1-b/ et0_tx_en/ rmii0_txd_en 71 pe7 d15[a15/d15] mtioc6a/ gtioc3a-e/toc1 mmc_res#-b/ sdhi_wp-b irq7 an105 72 pe6 d14[a14/d14] tioc6c/gtioc3b-e/ tic1 mmc_cd-b/ sdhi_cd-b irq6 an104 73 pe5 d13[a13/d13] mtioc4c/mtioc2b/ gtioc0a-a et0_rx_clk/ ref50ck0 irq5 an103 74 pe4 d12[a12/d12] mtioc4d/mtioc1a/ gtioc1a-a/po28 et0_erxd2 an102 75 pe3 d11[a11/d11] mtioc4b/ gtioc2a-a/po26/ poe8#/toc3 cts12#/rts12#/ ss12#/et0_erxd3 mmc_d7-b an101 76 pe2 d10[a10/d10] mtioc4a/ gtioc0b-a/po23/ tic3 rxd12/smiso12/ sscl12/rxdx12 mmc_d6-b irq7-ds an100 77 pe1 d9[a9/d9] mtioc4c/mtioc3b/ gtioc1b-a/po18 txd12/smosi12/ ssda12/txdx12/ siox12 mmc_d5-b anex1 78 pe0 d8[a8/d8] mtioc3d/ gtioc2b-a sck12 mmc_d4-b anex0 79 pd7 d7[a7/d7] mtic5u/poe0# mmc_d1-b/ sdhi_d1-b/ qio1-b/ qmi-b irq7 an107 80 pd6 d6[a6/d6] mtic5v/mtioc8a/ poe4# mmc_d0-b/ sdhi_d0-b/ qio0-b/ qmo-b irq6 an106 table 1.10 list of pin and pin functions (100-pin lqfp) (3/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
rx64m group 1. overview r01ds0173ej0100 rev.1.00 page 64 of 230 jul 31, 2014 81 pd5 d5[a5/d5] mtic5w/mtioc8c/ poe10# mmc_clk-b/ sdhi_clk-b/ qspclk-b irq5 an113 82 pd4 d4[a4/d4] mtioc8b/poe11# mmc_cmd-b/ sdhi_cmd-b/ qssl-b irq4 an112 83 pd3 d3[a3/d3] mtioc8d/ gtioc0a-e/poe8#/ toc2 mmc_d3-b/ sdhi_d3-b/ qio3-b irq3 an111 84 pd2 d2[a2/d2] mtioc4d/ gtioc0b-e/tic2 crx0 mmc_d2-b/ sdhi_d2-b/ qio2-b irq2 an110 85 pd1 d1[a1/d1] mtioc4b/ gtioc1a-e/poe0# ctx0 irq1 an109 86 pd0 d0[a0/d0] gtioc1b-e/poe4# irq0 an108 87 p47 irq15-ds an007 88 p46 irq14-ds an006 89 p45 irq13-ds an005 90 p44 irq12-ds an004 91 p43 irq11-ds an003 92 p42 irq10-ds an002 93 p41 irq9-ds an001 94 vrefl0 95 p40 irq8-ds an000 96 vrefh0 97 avcc0 98 p07 irq15 adtrg0# 99 avss0 100 p05 irq13 da1 table 1.10 list of pin and pin functions (100-pin lqfp) (4/4) pin number power supply clock system contro i/o port bus exdmac timer communication memory interface camera interface interrupt s12adc, r12da 100-pin lqfp (mtu, gpt, tpu, tmr, ppg, rtc, cmtw, poe, cac) (etherc, scig, scih, rspi, riic, can, usb, ssi) (qspi, sdhi, mmcif, pdc)
r01ds0173ej0100 rev.1.00 page 65 of 230 jul 31, 2014 rx64m group 2. cpu 2. cpu figure 2.1 shows register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register b31 b0 dsp instruction register b71 b0 acc0 (accumulator 0) acc1 (accumulator 1) usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) control register b31 b0 extb (exception table register)
r01ds0173ej0100 rev.1.00 page 66 of 230 jul 31, 2014 rx64m group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen 32-bit general-purpose registers (r0 to r15). r0 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (isp ) / user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack poi nter (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). (2) exception table register (extb) the exception table register (extb) specifies the address wher e the exception vector table starts. (3) interrupt table register (intb) the interrupt table register (int b) specifies the address where th e interrupt vector table starts. (4) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (5) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (6) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (7) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (8) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. (9) floating-point status word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (ej) enables the exception ha ndling (ej = 1), the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if the exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v).
r01ds0173ej0100 rev.1.00 page 67 of 230 jul 31, 2014 rx64m group 2. cpu 2.3 accumulator the accumulator (acc0 or acc1) is a 72-bit register used for dsp instruct ions. the accumulator is handled as a 96-bit register for reading and writing. at this time, when bits 95 to 72 of the accumulator are read , the value where the value of bit 71 is sign extended is read . writing to bits 95 to 72 of the accumulator is ignored. acc0 is also used for the multiply and multiply-and-accumulate in structions; emul, emulu, fmul, mul, and rmpa, in whic h case the prior value in acc0 is modified by execu tion of the instruction. use the mvtacgu, mvtachi, and mvtaclo instructi ons for writing to the accu mulator. the mvtacgu, mvtachi, and mvtaclo instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfacgu, mvfa chi, mvfacmi, and mvfaclo in structions for reading data from the accumulator. the mvfacgu, mvfachi, mvfacmi, and mvfaclo instructions r ead data from the guard bits (bits 95 to 64), higher- order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
r01ds0173ej0100 rev.1.00 page 68 of 230 jul 31, 2014 rx64m group 3. address space 3. address space 3.1 address space this mcu has a 4-gbyte address space, consisting of the range of addresses from 0000 0000h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will di ffer according to the operating mode and states of control bits. figure 3.1 memory map in each operating mode reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 on-chip ram external address space (cs area) reserved area* 3 external address space on-chip ram on-chip rom (program rom) (read only)* 2 on-chip rom (data flash memory) reserved area* 3 external address space (cs area) 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 on-chip ram on-chip rom (program rom) (read only)* 2 0010 0000h 0011 0000h on-chip rom (data flash memory) 0100 0000h ecc-ram ffc0 0000h on-chip rom (user boot) (read only) 0000 0000h 0008 0000h on-chip rom enabled extended mode 0010 0000h 0100 0000h 0800 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0100 0000h 0800 0000h ff00 0000h 00ff 8000h 00ff 8000h ff7f 8000h ff80 0000h on-chip rom (user boot) (read only) 1000 0000h external address space (sdram area) external address space (sdram area) 1000 0000h ecc-ram 0011 0000h ffff ffffh ffc0 0000h ff7f 8000h ff80 0000h ecc-ram 00ff 8000h ff00 0000h on-chip rom (fcu firmware) (read only)* 4 feff f000h on-chip rom (option-setting memory) 0012 0040h reserved area* 3 0012 0070h on-chip rom (write only)* 2 007e 0000h reserved area* 3 fcu-ram area* 4 reserved area* 3 peripheral i/o register 007f 0000h 007f 8000h 007f 9000h 007f e000h 0080 0000h reserved area* 3 reserved area* 3 on-chip rom (option-setting memory) 0012 0040h reserved area* 3 0012 0070h on-chip rom (write only)* 2 007e 0000h reserved area* 3 fcu-ram area* 4 reserved area* 3 peripheral i/o register 007f 0000h 007f 8000h 007f 9000h 007f e000h 0080 0000h reserved area* 3 ff00 0000h on-chip rom (fcu firmware) (read only)* 4 feff f000h peripheral i/o registers standby ram 000a 4000h peripheral i/o registers 000a 6000h peripheral i/o registers standby ram 000a 4000h peripheral i/o registers 000a 6000h peripheral i/o registers standby ram 000a 4000h peripheral i/o registers 000a 6000h note 1. the address space in boot mode and user boot mode/usb boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note 3. reserved areas should not be accessed. note 4. the fcu-ram and the on-chip rom (fcu firmware) are reserved in products that do not include the fcu-ram. for details on the fcu, see secti on 63, flash memory, in the rx64m group user?s manual: hardware . code flash memory capacity address data flash memory capacity address ram capacity address 4 mbytes ffc0 0000h to ffff ffffh 64 kbytes 0010 0000h to 0010 ffffh 512 kbytes 0000 0000h to 0007 ffffh 3 mbytes ffd0 0000h to ffff ffffh 2.5 mbytes ffd8 0000h to ffff ffffh 2 mbytes ffe0 0000h to ffff ffffh *2 *2 *2
r01ds0173ej0100 rev.1.00 page 69 of 230 jul 31, 2014 rx64m group 3. address space 3.2 external address space the external address space is divided in to cs areas (cs0 to cs7) and sdram area (sdcs). the cs areas are divided into up to eight areas (cs0 to cs7), each corresponding to the csn# signal output from a csn# (n = 0 to 7) pin. figure 3.2 shows the address ranges correspondi ng to the individual cs areas (cs0 to cs7) and sdram areas (sdcs) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) reserved area* 1 reserved area * 1 0000 0000h 0008 0000h ram external address space (cs area) 0010 0000h 0100 0000h 0800 0000h ff00 0000h external address space* 2 (cs area) 0100 0000h 0200 0000h 0300 0000h 0400 0000h 0500 0000h 0600 0000h 0700 0000h cs7 (16 mbytes) 01ff ffffh 02ff ffffh 03ff ffffh 04ff ffffh 05ff ffffh 06ff ffffh 07ff ffffh cs6 (16 mbytes) cs5 (16 mbytes) cs4 (16 mbytes) cs3 (16 mbytes) cs2 (16 mbytes) cs1 (16 mbytes) ffff ffffh ffff ffffh ff00 0000h cs0 (16 mbytes) external address space (sdram area) 1000 0000h 0fff ffffh 0800 0000h sdcs (128 mbytes) note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses above 1000 0000h is as shown in figure on this section, memory map in each operating mode. peripheral i/o registers standby ram 000a 4000h peripheral i/o registers 000a 6000h
r01ds0173ej0100 rev.1.00 page 70 of 230 jul 31, 2014 rx64m group 4. i/o registers 4. i/o registers this section gives information on the on-chip i/o register addr esses. the information is given as shown below. notes on writing to registers are also given at the end. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? the number of access cycles indicates the number of cycles based on the specified reference clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o re gister, the cpu starts executing the subsequent in struction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0173ej0100 rev.1.00 page 71 of 230 jul 31, 2014 rx64m group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for the number of i/o regist er access cycles, refer to section table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. *1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for inte rnal peripheral busses 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 or registers for the ex ternal bus control unit (except for bus error related registers) are accessed, the number of divided cloc k synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access states shown in table 4.1. when the frequency ratio of iclk is lower than that of pc lk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access fr om the cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmac or dtc). (4) restrictions in relation to rmpa and string-manipulation instructions the allocation of data to be handled by rmpa or string-man ipulation instructions to i/o registers is prohibited, and operation is not guaranteed if this restriction is not observed.
r01ds0173ej0100 rev.1.00 page 72 of 230 jul 31, 2014 rx64m group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk 0008 0000h syste m mode monitor register mdmonr 16 16 3 iclk operati ng modes 0008 0002h syste m mode status register mdsr 16 16 3 iclk operati ng modes 0008 0006h syste m system control register 0 syscr0 16 16 3 iclk operati ng modes 0008 0008h syste m system control register 1 syscr1 16 16 3 iclk operati ng modes 0008 000ch syste m standby control register sbycr 16 16 3 iclk low power consum ption 0008 0010h syste m module stop control register a mstpcra 32 32 3 iclk low power consum ption 0008 0014h syste m module stop control register b mstpcrb 32 32 3 iclk low power consum ption 0008 0018h syste m module stop control register c mstpcrc 32 32 3 iclk low power consum ption 0008 001ch syste m module stop control register d mstpcrd 32 32 3 iclk low power consum ption 0008 0020h syste m system clock control register sckcr 32 32 3 iclk clock generat ion circuit 0008 0024h syste m system clock control register 2 sckcr2 16 16 3 iclk clock generat ion circuit 0008 0026h syste m system clock control register 3 sckcr3 16 16 3 iclk clock generat ion circuit 0008 0028h syste m pll control register pllcr 16 16 3 iclk clock generat ion circuit 0008 002ah syste m pll control register 2 pllcr2 88 3 iclk clock generat ion circuit 0008 0030h syste m external bus clock control register bckcr 88 3 iclk clock generat ion circuit 0008 0032h syste m main clock oscillator control register mosccr 88 3 iclk clock generat ion circuit 0008 0033h syste m sub-clock oscillator control register sosccr 88 3 iclk clock generat ion circuit 0008 0034h syste m low-speed on-chip oscillator control register lococr 88 3 iclk clock generat ion circuit
r01ds0173ej0100 rev.1.00 page 73 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 0035h syste m iwdt-dedicated on-chip oscillator control register ilococr 88 3 iclk clock generat ion circuit 0008 0036h syste m high-speed on-chip oscillator control register hococr 88 3 iclk clock generat ion circuit 0008 0037h syste m high-speed on-chip oscillator control register 2 hococr2 88 3 iclk clock generat ion circuit 0008 003ch syste m oscillation stabilization flag register oscovfsr 88 3 iclk clock generat ion circuit 0008 0040h syste m oscillation stop detection control register ostdcr 88 3 iclk clock generat ion circuit 0008 0041h syste m oscillation stop detection status register ostdsr 88 3 iclk clock generat ion circuit 0008 00a0h syste m operating power control register opccr 88 3 iclk low power consum ption 0008 00a1h syste m sleep mode return clock source switching register rstckcr 88 3 iclk low power consum ption 0008 00a2h syste m main clock oscillator wait control register moscwtcr 88 3 iclk clock generat ion circuit 0008 00a3h syste m sub-clock oscillator wait control register soscwtcr 88 3 iclk clock generat ion circuit 0008 00c0h syste m reset status register 2 rstsr2 88 3 iclk resets 0008 00c2h syste m software reset register swrr 16 16 3 iclk resets 0008 00e0h syste m voltage monitoring 1 circuit control register 1 lvd1cr1 88 3 iclk ldva 0008 00e1h syste m voltage monitoring 1 circuit status register lvd1sr 88 3 iclk ldva 0008 00e2h syste m voltage monitoring 2 circuit control register 1 lvd2cr1 88 3 iclk ldva 0008 00e3h syste m voltage monitoring 2 circuit status register lvd2sr 88 3 iclk ldva 0008 03feh syste m protect register prcr 16 16 3 iclk register write protecti on functio n 0008 12c0h eccra m eccram operating mode control register eccrammod e 8 8 2 iclk ram 0008 12c1h eccra m eccram 2-bit error status register eccram2sts 8 8 2 iclk ram 0008 12c2h eccra m eccram 1-bit error information update enable register eccram1sts en 8 8 2 iclk ram 0008 12c3h eccra m eccram 1-bit error status register eccram1sts 8 8 2 iclk ram 0008 12c4h eccra m eccram protection register eccramprcr 8 8 2 iclk ram 0008 12c8h eccra m eccram 2-bit error address capture register eccram2eca d 32 32 2 iclk ram table 4.1 list of i/o register s (address order) (2 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 74 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 12cch eccra m eccram 1-bit error address capture register eccram1eca d 32 32 2 iclk ram 0008 12d0h eccra m eccram protection register 2 eccramprcr 2 8 8 2 iclk ram 0008 12d4h eccra m eccram test control register eccrametst 8 8 2 iclk ram 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk buses 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk buses 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk buses 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk buses 0008 1310h bsc bus priority control register buspri 16 16 2 iclk buses 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk dmaca 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk dmaca 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk dmaca 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk dmaca 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk dmaca 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk dmaca 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk dmaca 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk dmaca 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk dmaca 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk dmaca 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk dmaca 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk dmaca 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk dmaca 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk dmaca 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk dmaca 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk dmaca table 4.1 list of i/o register s (address order) (3 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 75 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk dmaca 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk dmaca 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk dmaca 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2100h dmac4 dma source address register dmsar 32 32 2 iclk dmaca 0008 2104h dmac4 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2108h dmac4 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 210ch dmac4 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2110h dmac4 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2113h dmac4 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2114h dmac4 dma address mode register dmamd 16 16 2 iclk dmaca 0008 211ch dmac4 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 211dh dmac4 dma software start register dmreq 8 8 2 iclk dmaca 0008 211eh dmac4 dma status register dmsts 8 8 2 iclk dmaca 0008 211fh dmac4 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2140h dmac5 dma source address register dmsar 32 32 2 iclk dmaca 0008 2144h dmac5 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2148h dmac5 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 214ch dmac5 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2150h dmac5 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2153h dmac5 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2154h dmac5 dma address mode register dmamd 16 16 2 iclk dmaca 0008 215ch dmac5 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 215dh dmac5 dma software start register dmreq 8 8 2 iclk dmaca 0008 215eh dmac5 dma status register dmsts 8 8 2 iclk dmaca 0008 215fh dmac5 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2180h dmac6 dma source address register dmsar 32 32 2 iclk dmaca 0008 2184h dmac6 dma destination address register dmdar 32 32 2 iclk dmaca 0008 2188h dmac6 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 218ch dmac6 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 2190h dmac6 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 2193h dmac6 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 2194h dmac6 dma address mode register dmamd 16 16 2 iclk dmaca 0008 219ch dmac6 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 219dh dmac6 dma software start register dmreq 8 8 2 iclk dmaca 0008 219eh dmac6 dma status register dmsts 8 8 2 iclk dmaca 0008 219fh dmac6 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 21c0h dmac7 dma source address register dmsar 32 32 2 iclk dmaca 0008 21c4h dmac7 dma destination address register dmdar 32 32 2 iclk dmaca 0008 21c8h dmac7 dma transfer count register dmcra 32 32 2 iclk dmaca 0008 21cch dmac7 dma block transfer count register dmcrb 16 16 2 iclk dmaca 0008 21d0h dmac7 dma transfer mode register dmtmd 16 16 2 iclk dmaca 0008 21d3h dmac7 dma interrupt setting register dmint 8 8 2 iclk dmaca 0008 21d4h dmac7 dma address mode register dmamd 16 16 2 iclk dmaca 0008 21dch dmac7 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 21ddh dmac7 dma software start register dmreq 8 8 2 iclk dmaca 0008 21deh dmac7 dma status register dmsts 8 8 2 iclk dmaca 0008 21dfh dmac7 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2200h dmac dmaca module activation register dmast 8 8 2 iclk dmaca table 4.1 list of i/o register s (address order) (4 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 76 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 2204h dmac dmac74 interrupt status monitor register dmist 8 8 2 iclk dmaca 0008 2400h dtc dtc control register dtccr 8 8 2 iclk dtca 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk dtca 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk dtca 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk dtca 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk dtca 0008 2800h exdma c0 exdma source address register edmsar 32 32 1, 2 bclk exdma ca 0008 2804h exdma c0 exdma destination address register edmdar 32 32 1, 2 bclk exdma ca 0008 2808h exdma c0 exdma transfer count register edmcra 32 32 1, 2 bclk exdma ca 0008 280ch exdma c0 exdma block transfer count register edmcrb 16 16 1, 2 bclk exdma ca 0008 2810h exdma c0 exdma transfer mode register edmtmd 16 16 1, 2 bclk exdma ca 0008 2812h exdma c0 exdma output setting register edmomd 8 8 1, 2 bclk exdma ca 0008 2813h exdma c0 exdma interrupt setting register edmint 8 8 1, 2 bclk exdma ca 0008 2814h exdma c0 exdma address mode register edmamd 32 32 1, 2 bclk exdma ca 0008 2818h exdma c0 exdma offset register edmofr 32 32 1, 2 bclk exdma ca 0008 281ch exdma c0 exdma transfer enable register edmcnt 8 8 1, 2 bclk exdma ca 0008 281dh exdma c0 exdma software start register edmreq 8 8 1, 2 bclk exdma ca 0008 281eh exdma c0 exdma status register edmsts 8 8 1, 2 bclk exdma ca 0008 2820h exdma c0 exdma external request sense mode register edmrmd 8 8 1, 2 bclk exdma ca 0008 2821h exdma c0 exdma external request flag register edmerf 8 8 1, 2 bclk exdma ca 0008 2822h exdma c0 exdma peripheral request flag register edmprf 8 8 1, 2 bclk exdma ca 0008 2840h exdma c1 exdma source address register edmsar 32 32 1, 2 bclk exdma ca 0008 2844h exdma c1 exdma destination address register edmdar 32 32 1, 2 bclk exdma ca 0008 2848h exdma c1 exdma transfer count register edmcra 32 32 1, 2 bclk exdma ca 0008 284ch exdma c1 exdma block transfer count register edmcrb 16 16 1, 2 bclk exdma ca 0008 2850h exdma c1 exdma transfer mode register edmtmd 16 16 1, 2 bclk exdma ca 0008 2852h exdma c1 exdma output setting register edmomd 8 8 1, 2 bclk exdma ca 0008 2853h exdma c1 exdma interrupt setting register edmint 8 8 1, 2 bclk exdma ca 0008 2854h exdma c1 exdma address mode register edmamd 32 32 1, 2 bclk exdma ca 0008 285ch exdma c1 exdma transfer enable register edmcnt 8 8 1, 2 bclk exdma ca 0008 285dh exdma c1 exdma software start register edmreq 8 8 1, 2 bclk exdma ca 0008 285eh exdma c1 exdma status register edmsts 8 8 1, 2 bclk exdma ca 0008 2860h exdma c1 exdma external request sense mode register edmrmd 8 8 1, 2 bclk exdma ca 0008 2861h exdma c1 exdma external request flag register edmerf 8 8 1, 2 bclk exdma ca table 4.1 list of i/o register s (address order) (5 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 77 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 2862h exdma c1 exdma peripheral request flag register edmprf 8 8 1, 2 bclk exdma ca 0008 2a00h exdma c exdma module start register edmast 8 8 1, 2 bclk exdma ca 0008 2be0h exdma c cluster buffer register 0 clsbr0 32 32 1, 2 bclk exdma ca 0008 2be4h exdma c cluster buffer register 1 clsbr1 32 32 1, 2 bclk exdma ca 0008 2be8h exdma c cluster buffer register 2 clsbr2 32 32 1, 2 bclk exdma ca 0008 2bech exdma c cluster buffer register 3 clsbr3 32 32 1, 2 bclk exdma ca 0008 2bf0h exdma c cluster buffer register 4 clsbr4 32 32 1, 2 bclk exdma ca 0008 2bf4h exdma c cluster buffer register 5 clsbr5 32 32 1, 2 bclk exdma ca 0008 2bf8h exdma c cluster buffer register 6 clsbr6 32 32 1, 2 bclk exdma ca 0008 2bfch exdma c cluster buffer register 7 clsbr7 32 32 1, 2 bclk exdma ca 0008 3002h bsc cs0 mode register cs0mod 16 16 1, 2 bclk buses 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1, 2 bclk buses 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1, 2 bclk buses 0008 3012h bsc cs1 mode register cs1mod 16 16 1, 2 bclk buses 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1, 2 bclk buses 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1, 2 bclk buses 0008 3022h bsc cs2 mode register cs2mod 16 16 1, 2 bclk buses 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1, 2 bclk buses 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1, 2 bclk buses 0008 3032h bsc cs3 mode register cs3mod 16 16 1, 2 bclk buses 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1, 2 bclk buses 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1, 2 bclk buses 0008 3042h bsc cs4 mode register cs4mod 16 16 1, 2 bclk buses 0008 3044h bsc cs4 wait control register 1 cs4wcr1 32 32 1, 2 bclk buses 0008 3048h bsc cs4 wait control register 2 cs4wcr2 32 32 1, 2 bclk buses 0008 3052h bsc cs5 mode register cs5mod 16 16 1, 2 bclk buses 0008 3054h bsc cs5 wait control register 1 cs5wcr1 32 32 1, 2 bclk buses 0008 3058h bsc cs5 wait control register 2 cs5wcr2 32 32 1, 2 bclk buses 0008 3062h bsc cs6 mode register cs6mod 16 16 1, 2 bclk buses 0008 3064h bsc cs6 wait control register 1 cs6wcr1 32 32 1, 2 bclk buses 0008 3068h bsc cs6 wait control register 2 cs6wcr2 32 32 1, 2 bclk buses 0008 3072h bsc cs7 mode register cs7mod 16 16 1, 2 bclk buses 0008 3074h bsc cs7 wait control register 1 cs7wcr1 32 32 1, 2 bclk buses 0008 3078h bsc cs7 wait control register 2 cs7wcr2 32 32 1, 2 bclk buses 0008 3802h bsc cs0 control register cs0cr 16 16 1, 2 bclk buses 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1, 2 bclk buses 0008 3812h bsc cs1 control register cs1cr 16 16 1, 2 bclk buses 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1, 2 bclk buses 0008 3822h bsc cs2 control register cs2cr 16 16 1, 2 bclk buses 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1, 2 bclk buses 0008 3832h bsc cs3 control register cs3cr 16 16 1, 2 bclk buses 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1, 2 bclk buses 0008 3842h bsc cs4 control register cs4cr 16 16 1, 2 bclk buses 0008 384ah bsc cs4 recovery cycle register cs4rec 16 16 1, 2 bclk buses table 4.1 list of i/o register s (address order) (6 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 78 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 3852h bsc cs5 control register cs5cr 16 16 1, 2 bclk buses 0008 385ah bsc cs5 recovery cycle register cs5rec 16 16 1, 2 bclk buses 0008 3862h bsc cs6 control register cs6cr 16 16 1, 2 bclk buses 0008 386ah bsc cs6 recovery cycle register cs6rec 16 16 1, 2 bclk buses 0008 3872h bsc cs7 control register cs7cr 16 16 1, 2 bclk buses 0008 387ah bsc cs7 recovery cycle register cs7rec 16 16 1, 2 bclk buses 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1, 2 bclk buses 0008 3c00h bsc sdc control register sdccr 8 8 1, 2 bclk buses 0008 3c01h bsc sdc mode register sdcmod 8 8 1, 2 bclk buses 0008 3c02h bsc sdram access mode register sdamod 8 8 1, 2 bclk buses 0008 3c10h bsc sdram self-refresh control register sdself 8 8 1, 2 bclk buses 0008 3c14h bsc sdram refresh control register sdrfcr 16 16 1, 2 bclk buses 0008 3c16h bsc sdram auto-refresh control register sdrfen 8 8 1, 2 bclk buses 0008 3c20h bsc sdram initialization sequence control register sdicr 8 8 1, 2 bclk buses 0008 3c24h bsc sdram initialization register sdir 16 16 1, 2 bclk buses 0008 3c40h bsc sdram address register sdadr 8 8 1, 2 bclk buses 0008 3c44h bsc sdram timing register sdtr 32 32 1, 2 bclk buses 0008 3c48h bsc sdram mode register sdmod 16 16 1, 2 bclk buses 0008 3c50h bsc sdram status register sdsr 8 8 1, 2 bclk buses 0008 6400h mpu region-0 start page number register rspage0 32 32 1 iclk mpu 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk mpu 0008 6408h mpu region-1 start page number register rspage1 32 32 1 iclk mpu 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk mpu 0008 6410h mpu region-2 start page number register rspage2 32 32 1 iclk mpu 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk mpu 0008 6418h mpu region-3 start page number register rspage3 32 32 1 iclk mpu 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk mpu 0008 6420h mpu region-4 start page number register rspage4 32 32 1 iclk mpu 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk mpu 0008 6428h mpu region-5 start page number register rspage5 32 32 1 iclk mpu 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk mpu 0008 6430h mpu region-6 start page number register rspage6 32 32 1 iclk mpu 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk mpu 0008 6438h mpu region-7 start page number register rspage7 32 32 1 iclk mpu 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk mpu 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk mpu 0008 6504h mpu background access control register mpbac 32 32 1 iclk mpu 0008 6508h mpu memory-protection error status-clearing register mpeclr 32 32 1 iclk mpu 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk mpu 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk mpu 0008 6520h mpu region search address register mpsa 32 32 1 iclk mpu 0008 6524h mpu region search operation register mpops 16 16 1 iclk mpu 0008 6526h mpu region invalidation operation register mpopi 16 16 1 iclk mpu 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk mpu 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk mpu 0008 7010h to 0008 70ffh icu interrupt request registers 016 to 255 ir016 to 255 8 8 2 iclk icua 0008 711ah to 0008 71ffh icu dtc start enable registers 026 to 255 dtcer026 to dtcer255 8 8 2 iclk icua 0008 7202h to 0008 721fh icu interrupt request enable registers 02 to 1f ier02 to ier1f 8 8 2 iclk icua table 4.1 list of i/o register s (address order) (7 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 79 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 72e0h icu software interrupt generation register swintr 8 8 2 iclk icua 0008 72e1h icu software interrupt 2 generation register swint2r 8 8 2 iclk icua 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk icua 0008 7300h to 0008 73ffh icu interrupt source priority registers 000 to 255 ipr000 to ipr255 8 8 2 iclk icua 0008 7400h icu dmac start source select register 0 dmrsr0 8 8 2 iclk icua 0008 7404h icu dmac start source select register 1 dmrsr1 8 8 2 iclk icua 0008 7408h icu dmac start source select register 2 dmrsr2 8 8 2 iclk icua 0008 740ch icu dmac start source select register 3 dmrsr3 8 8 2 iclk icua 0008 7410h icu dmac start source select register 4 dmrsr4 8 8 2 iclk icua 0008 7414h icu dmac start source select register 5 dmrsr5 8 8 2 iclk icua 0008 7418h icu dmac start source select register 6 dmrsr6 8 8 2 iclk icua 0008 741ch icu dmac start source select register 7 dmrsr7 8 8 2 iclk icua 0008 7500h to 0008 750fh icu irq control registers 0 to 15 irqcr0 to 15 8 8 2 iclk icua 0008 7520h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk icua 0008 7521h icu irq pin digital filter enable register 1 irqflte1 8 8 2 iclk icua 0008 7528h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk icua 0008 752ah icu irq pin digital filter setting register 1 irqfltc1 16 16 2 iclk icua 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk icua 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk icua 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk icua 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk icua 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk icua 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk icua 0008 7600h icu group be0 interrupt request register grpbe0 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7630h icu group be0 interrupt request register grpbl0 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7634h icu group bl1 interrupt request register grpbl1 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7640h icu group be0 interrupt request enable register genbe0 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7670h icu group bl0 interrupt request enable register genbl0 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7674h icu group bl1 interrupt request enable register genbl1 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7680h icu group be0 interrupt clear register gcrbe0 32 32 2 iclk to 1 pclkb 2 iclk icua 0008 7700h icu software configurable interrupt b request register 0 pibr0 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7701h icu software configurable interrupt b request register 1 pibr1 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7702h icu software configurable interrupt b request register 2 pibr2 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7703h icu software configurable interrupt b request register 3 pibr3 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7704h icu software configurable interrupt b request register 4 pibr4 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7705h icu software configurable interrupt b request register 5 pibr5 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7706h icu software configurable interrupt b request register 6 pibr6 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7707h icu software configurable interrupt b request register 7 pibr7 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7708h icu software configurable interrupt b request register 8 pibr8 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7709h icu software configurable interrupt b request register 9 pibr9 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 770ah icu software configurable interrupt b request register a pibra 8 8 2 iclk to 1 pclkb 2 iclk icua table 4.1 list of i/o register s (address order) (8 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 80 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 7780h icu software configurable interrupt b select register 128 slibxr128 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7781h icu software configurable interrupt b select register 129 slibxr129 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7782h icu software configurable interrupt b select register 130 slibxr130 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7783h icu software configurable interrupt b select register 131 slibxr131 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7784h icu software configurable interrupt b select register 132 slibxr132 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7785h icu software configurable interrupt b select register 133 slibxr133 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7786h icu software configurable interrupt b select register 134 slibxr134 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7787h icu software configurable interrupt b select register 135 slibxr135 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7788h icu software configurable interrupt b select register 136 slibxr136 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7789h icu software configurable interrupt b select register 137 slibxr137 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778ah icu software configurable interrupt b select register 138 slibxr138 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778bh icu software configurable interrupt b select register 139 slibxr139 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778ch icu software configurable interrupt b select register 140 slibxr140 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778dh icu software configurable interrupt b select register 141 slibxr141 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778eh icu software configurable interrupt b select register 142 slibxr142 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 778fh icu software configurable interrupt b select register 143 slibxr143 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7790h icu software configurable interrupt b select register 144 slibr144 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7791h icu software configurable interrupt b select register 145 slibr145 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7792h icu software configurable interrupt b select register 146 slibr146 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7793h icu software configurable interrupt b select register 147 slibr147 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7794h icu software configurable interrupt b select register 148 slibr148 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7795h icu software configurable interrupt b select register 149 slibr149 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7796h icu software configurable interrupt b select register 150 slibr150 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7797h icu software configurable interrupt b select register 151 slibr151 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7798h icu software configurable interrupt b select register 152 slibr152 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7799h icu software configurable interrupt b select register 153 slibr153 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779ah icu software configurable interrupt b select register 154 slibr154 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779bh icu software configurable interrupt b select register 155 slibr155 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779ch icu software configurable interrupt b select register 156 slibr156 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779dh icu software configurable interrupt b select register 157 slibr157 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779eh icu software configurable interrupt b select register 158 slibr158 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 779fh icu software configurable interrupt b select register 159 slibr159 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a0h icu software configurable interrupt b select register 160 slibr160 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a1h icu software configurable interrupt b select register 161 slibr161 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a2h icu software configurable interrupt b select register 162 slibr162 8 8 2 iclk to 1 pclkb 2 iclk icua table 4.1 list of i/o register s (address order) (9 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 81 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 77a3h icu software configurable interrupt b select register 163 slibr163 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a4h icu software configurable interrupt b select register 164 slibr164 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a5h icu software configurable interrupt b select register 165 slibr165 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a6h icu software configurable interrupt b select register 166 slibr166 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a7h icu software configurable interrupt b select register 167 slibr167 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a8h icu software configurable interrupt b select register 168 slibr168 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77a9h icu software configurable interrupt b select register 169 slibr169 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77aah icu software configurable interrupt b select register 170 slibr170 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77abh icu software configurable interrupt b select register 171 slibr171 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77ach icu software configurable interrupt b select register 172 slibr172 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77adh icu software configurable interrupt b select register 173 slibr173 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77aeh icu software configurable interrupt b select register 174 slibr174 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77afh icu software configurable interrupt b select register 175 slibr175 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b0h icu software configurable interrupt b select register 176 slibr176 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b1h icu software configurable interrupt b select register 177 slibr177 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b2h icu software configurable interrupt b select register 178 slibr178 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b3h icu software configurable interrupt b select register 179 slibr179 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b4h icu software configurable interrupt b select register 180 slibr180 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b5h icu software configurable interrupt b select register 181 slibr181 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b6h icu software configurable interrupt b select register 182 slibr182 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b7h icu software configurable interrupt b select register 183 slibr183 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b8h icu software configurable interrupt b select register 184 slibr184 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77b9h icu software configurable interrupt b select register 185 slibr185 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77bah icu software configurable interrupt b select register 186 slibr186 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77bbh icu software configurable interrupt b select register 187 slibr187 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77bch icu software configurable interrupt b select register 188 slibr188 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77bdh icu software configurable interrupt b select register 189 slibr189 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77beh icu software configurable interrupt b select register 190 slibr190 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77bfh icu software configurable interrupt b select register 191 slibr191 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c0h icu software configurable interrupt b select register 192 slibr192 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c1h icu software configurable interrupt b select register 193 slibr193 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c2h icu software configurable interrupt b select register 194 slibr194 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c3h icu software configurable interrupt b select register 195 slibr195 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c4h icu software configurable interrupt b select register 196 slibr196 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c5h icu software configurable interrupt b select register 197 slibr197 8 8 2 iclk to 1 pclkb 2 iclk icua table 4.1 list of i/o register s (address order) (10 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 82 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 77c6h icu software configurable interrupt b select register 198 slibr198 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c7h icu software configurable interrupt b select register 199 slibr199 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c8h icu software configurable interrupt b select register 200 slibr200 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77c9h icu software configurable interrupt b select register 201 slibr201 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77cah icu software configurable interrupt b select register 202 slibr202 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77cbh icu software configurable interrupt b select register 203 slibr203 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77cch icu software configurable interrupt b select register 204 slibr204 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77cdh icu software configurable interrupt b select register 205 slibr205 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77ceh icu software configurable interrupt b select register 206 slibr206 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 77cfh icu software configurable interrupt b select register 207 slibr207 8 8 2 iclk to 1 pclkb 2 iclk icua 0008 7830h icu group al0 interrupt request register grpal0 32 32 2 iclk to 1 pclka 2 iclk icua 0008 7834h icu group al1 interrupt request register grpal1 32 32 2 iclk to 1 pclka 2 iclk icua 0008 7870h icu group al0 interrupt request enable register genal0 32 32 2 iclk to 1 pclka 2 iclk icua 0008 7874h icu group al1 interrupt request enable register genal1 32 32 2 iclk to 1 pclka 2 iclk icua 0008 7900h icu software configurable interrupt a request register 0 piar0 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7901h icu software configurable interrupt a request register 1 piar1 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7902h icu software configurable interrupt a request register 2 piar2 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7903h icu software configurable interrupt a request register 3 piar3 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7904h icu software configurable interrupt a request register 4 piar4 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7905h icu software configurable interrupt a request register 5 piar5 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7906h icu software configurable interrupt a request register 6 piar6 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7907h icu software configurable interrupt a request register 7 piar7 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7908h icu software configurable interrupt a request register 8 piar8 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7909h icu software configurable interrupt a request register 9 piar9 8 8 2 iclk to 1 pclka 2 iclk icua 0008 790ah icu software configurable interrupt a request register a piara 8 8 2 iclk to 1 pclka 2 iclk icua 0008 790bh icu software configurable interrupt a request register b piarb 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d0h icu software configurable interrupt a select register 208 sliar208 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d1h icu software configurable interrupt a select register 209 sliar209 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d2h icu software configurable interrupt a select register 210 sliar210 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d3h icu software configurable interrupt a select register 211 sliar211 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d4h icu software configurable interrupt a select register 212 sliar212 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d5h icu software configurable interrupt a select register 213 sliar213 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d6h icu software configurable interrupt a select register 214 sliar214 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d7h icu software configurable interrupt a select register 215 sliar215 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79d8h icu software configurable interrupt a select register 216 sliar216 8 8 2 iclk to 1 pclka 2 iclk icua table 4.1 list of i/o register s (address order) (11 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 83 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 79d9h icu software configurable interrupt a select register 217 sliar217 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79dah icu software configurable interrupt a select register 218 sliar218 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79dbh icu software configurable interrupt a select register 219 sliar219 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79dch icu software configurable interrupt a select register 220 sliar220 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79ddh icu software configurable interrupt a select register 221 sliar221 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79deh icu software configurable interrupt a select register 222 sliar222 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79dfh icu software configurable interrupt a select register 223 sliar223 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e0h icu software configurable interrupt a select register 224 sliar224 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e1h icu software configurable interrupt a select register 225 sliar225 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e2h icu software configurable interrupt a select register 226 sliar226 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e3h icu software configurable interrupt a select register 227 sliar227 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e4h icu software configurable interrupt a select register 228 sliar228 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e5h icu software configurable interrupt a select register 229 sliar229 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e6h icu software configurable interrupt a select register 230 sliar230 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e7h icu software configurable interrupt a select register 231 sliar231 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e8h icu software configurable interrupt a select register 232 sliar232 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79e9h icu software configurable interrupt a select register 233 sliar233 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79eah icu software configurable interrupt a select register 234 sliar234 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79ebh icu software configurable interrupt a select register 235 sliar235 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79ech icu software configurable interrupt a select register 236 sliar236 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79edh icu software configurable interrupt a select register 237 sliar237 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79eeh icu software configurable interrupt a select register 238 sliar238 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79efh icu software configurable interrupt a select register 239 sliar239 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f0h icu software configurable interrupt a select register 240 sliar240 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f1h icu software configurable interrupt a select register 241 sliar241 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f2h icu software configurable interrupt a select register 242 sliar242 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f3h icu software configurable interrupt a select register 243 sliar243 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f4h icu software configurable interrupt a select register 244 sliar244 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f5h icu software configurable interrupt a select register 245 sliar245 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f6h icu software configurable interrupt a select register 246 sliar246 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f7h icu software configurable interrupt a select register 247 sliar247 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f8h icu software configurable interrupt a select register 248 sliar248 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79f9h icu software configurable interrupt a select register 249 sliar249 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79fah icu software configurable interrupt a select register 250 sliar250 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79fbh icu software configurable interrupt a select register 251 sliar251 8 8 2 iclk to 1 pclka 2 iclk icua table 4.1 list of i/o register s (address order) (12 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 84 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 79fch icu software configurable interrupt a select register 252 sliar252 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79fdh icu software configurable interrupt a select register 253 sliar253 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79feh icu software configurable interrupt a select register 254 sliar254 8 8 2 iclk to 1 pclka 2 iclk icua 0008 79ffh icu software configurable interrupt a select register 255 sliar255 8 8 2 iclk to 1 pclka 2 iclk icua 0008 7a00h icu software configurable interrupt selection write protect register sliprcr 8 8 2 iclk to 1 pclka/b 2 iclk icua 0008 7a01h icu exdmac start interrupt select register selexdr 8 8 2 iclk to 1 pclka/b 2 iclk icua 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2, 3 pclkb 2 iclk cmt 0008 8002h cmt0 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk cmt 0008 8004h cmt0 compare match counter cmcnt 16 16 2, 3 pclkb 2 iclk cmt 0008 8006h cmt0 compare match constant register cmcor 16 16 2, 3 pclkb 2 iclk cmt 0008 8008h cmt1 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk cmt 0008 800ah cmt1 compare match counter cmcnt 16 16 2, 3 pclkb 2 iclk cmt 0008 800ch cmt1 compare match constant register cmcor 16 16 2, 3 pclkb 2 iclk cmt 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2, 3 pclkb 2 iclk cmt 0008 8012h cmt2 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk cmt 0008 8014h cmt2 compare match counter cmcnt 16 16 2, 3 pclkb 2 iclk cmt 0008 8016h cmt2 compare match constant register cmcor 16 16 2, 3 pclkb 2 iclk cmt 0008 8018h cmt3 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk cmt 0008 801ah cmt3 compare match counter cmcnt 16 16 2, 3 pclkb 2 iclk cmt 0008 801ch cmt3 compare match constant register cmcor 16 16 2, 3 pclkb 2 iclk cmt 0008 8020h wdt wdt refresh register wdtrr 8 8 2, 3 pclkb 2 iclk wdta 0008 8022h wdt wdt control register wdtcr 16 16 2, 3 pclkb 2 iclk wdta 0008 8024h wdt wdt status register wdtsr 16 16 2, 3 pclkb 2 iclk wdta 0008 8026h wdt wdt reset control register wdtrcr 8 8 2, 3 pclkb 2 iclk wdta 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2, 3 pclkb 2 iclk iwdta 0008 8032h iwdt iwdt control register iwdtcr 16 16 2, 3 pclkb 2 iclk iwdta 0008 8034h iwdt iwdt status register iwdtsr 16 16 2, 3 pclkb 2 iclk iwdta 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2, 3 pclkb 2 iclk iwdta 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2, 3 pclkb 2 iclk iwdta 0008 8040h da d/a data register 0 dadr0 16 16 2, 3 pclkb 2 iclk r12da 0008 8042h da d/a data register 1 dadr1 16 16 2, 3 pclkb 2 iclk r12da 0008 8044h da d/a control register dacr 8 8 2, 3 pclkb 2 iclk r12da 0008 8045h da dadrm format select register dadpr 8 8 2, 3 pclkb 2 iclk r12da 0008 8046h da d/a a/d synchronous start control register daadscr 8 8 2, 3 pclkb 2 iclk r12da 0008 8048h da d/a output amplifier control register daampcr 8 8 2, 3 pclkb 2 iclk r12da 0008 8100h tpua timer start register tstr 8 8 2, 3 pclkb 2 iclk tpua 0008 8101h tpua timer synchronous register tsyr 8 8 2, 3 pclkb 2 iclk tpua 0008 8108h tpu0 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8109h tpu1 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 810ah tpu2 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 810bh tpu3 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 810ch tpu4 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 810dh tpu5 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8110h tpu0 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8111h tpu0 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8112h tpu0 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk tpua 0008 8113h tpu0 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk tpua table 4.1 list of i/o register s (address order) (13 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 85 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 8114h tpu0 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8115h tpu0 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8116h tpu0 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8118h tpu0 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 811ah tpu0 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua 0008 811ch tpu0 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk tpua 0008 811eh tpu0 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk tpua 0008 8120h tpu1 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8121h tpu1 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8122h tpu1 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk tpua 0008 8124h tpu1 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8125h tpu1 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8126h tpu1 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8128h tpu1 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 812ah tpu1 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua 0008 8130h tpu2 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8131h tpu2 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8132h tpu2 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk tpua 0008 8134h tpu2 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8135h tpu2 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8136h tpu2 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8138h tpu2 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 813ah tpu2 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua 0008 8140h tpu3 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8141h tpu3 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8142h tpu3 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk tpua 0008 8143h tpu3 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk tpua 0008 8144h tpu3 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8145h tpu3 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8146h tpu3 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8148h tpu3 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 814ah tpu3 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua 0008 814ch tpu3 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk tpua 0008 814eh tpu3 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk tpua 0008 8150h tpu4 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8151h tpu4 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8152h tpu4 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk tpua 0008 8154h tpu4 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8155h tpu4 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8156h tpu4 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8158h tpu4 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 815ah tpu4 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua 0008 8160h tpu5 timer control register tcr 8 8 2, 3 pclkb 2 iclk tpua 0008 8161h tpu5 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk tpua 0008 8162h tpu5 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk tpua 0008 8164h tpu5 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk tpua 0008 8165h tpu5 timer status register tsr 8 8 2, 3 pclkb 2 iclk tpua 0008 8166h tpu5 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tpua 0008 8168h tpu5 timer general register a tgra 16 16 2, 3 pclkb 2 iclk tpua 0008 816ah tpu5 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk tpua table 4.1 list of i/o register s (address order) (14 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 86 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 81e6h ppg0 ppg output control register pcr 8 8 2, 3 pclkb 2 iclk ppg 0008 81e7h ppg0 ppg output mode register pmr 8 8 2, 3 pclkb 2 iclk ppg 0008 81e8h ppg0 next data enable registers h nderh 8 8 2, 3 pclkb 2 iclk ppg 0008 81e9h ppg0 next data enable registers l nderl 8 8 2, 3 pclkb 2 iclk ppg 0008 81eah ppg0 output data registers h podrh 8 8 2, 3 pclkb 2 iclk ppg 0008 81ebh ppg0 output data registers l podrl 8 8 2, 3 pclkb 2 iclk ppg 0008 81ech ppg0 next data registers h* 1 ndrh 8 8 2, 3 pclkb 2 iclk ppg 0008 81edh ppg0 next data registers l* 2 ndrl 8 8 2, 3 pclkb 2 iclk ppg 0008 81eeh ppg0 next data registers h* 1 ndrh2 8 8 2, 3 pclkb 2 iclk ppg 0008 81efh ppg0 next data registers l* 2 ndrl2 8 8 2, 3 pclkb 2 iclk ppg 0008 81f0h ppg1 ppg trigger select register ptrslr 8 8 2, 3 pclkb 2 iclk ppg 0008 81f6h ppg1 ppg output control register pcr 8 8 2, 3 pclkb 2 iclk ppg 0008 81f7h ppg1 ppg output mode register pmr 8 8 2, 3 pclkb 2 iclk ppg 0008 81f8h ppg1 next data enable registers h nderh 8 8 2, 3 pclkb 2 iclk ppg 0008 81f9h ppg1 next data enable registers l nderl 8 8 2, 3 pclkb 2 iclk ppg 0008 81fah ppg1 output data registers h podrh 8 8 2, 3 pclkb 2 iclk ppg 0008 81fbh ppg1 output data registers l podrl 8 8 2, 3 pclkb 2 iclk ppg 0008 81fch ppg1 next data registers h* 3 ndrh 8 8 2, 3 pclkb 2 iclk ppg 0008 81fdh ppg1 next data registers l* 4 ndrl 8 8 2, 3 pclkb 2 iclk ppg 0008 81feh ppg1 next data registers h* 3 ndrh2 8 8 2, 3 pclkb 2 iclk ppg 0008 81ffh ppg1 next data registers l* 4 ndrl2 8 8 2, 3 pclkb 2 iclk ppg 0008 8200h tmr0 timer control register tcr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8201h tmr1 timer control register tcr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8202h tmr0 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8203h tmr1 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8204h tmr0 time constant register a tcora 8 8 2, 3 pclkb 2 iclk tmrb 0008 8204h tmr01 time constant register a tcora 16 16 2, 3 pclkb 2 iclk tmrb 0008 8205h tmr1 time constant register a tcora 8 8 2, 3 pclkb 2 iclk tmrb 0008 8206h tmr0 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk tmrb 0008 8206h tmr01 time constant register b tcorb 16 16 2, 3 pclkb 2 iclk tmrb 0008 8207h tmr1 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk tmrb 0008 8208h tmr0 timer counter tcnt 8 8 2, 3 pclkb 2 iclk tmrb 0008 8208h tmr01 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tmrb 0008 8209h tmr1 timer counter tcnt 8 8 2, 3 pclkb 2 iclk tmrb 0008 820ah tmr0 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk tmrb 0008 820ah tmr01 timer counter control register tccr 16 16 2, 3 pclkb 2 iclk tmrb 0008 820bh tmr1 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk tmrb 0008 820ch tmr0 time count start register tcstr 8 8 2, 3 pclkb 2 iclk tmrb 0008 820dh tmr1 time count start register tcstr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8210h tmr2 timer control register tcr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8211h tmr3 timer control register tcr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8212h tmr2 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8213h tmr3 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8214h tmr2 time constant register a tcora 8 8 2, 3 pclkb 2 iclk tmrb 0008 8214h tmr23 time constant register a tcora 16 16 2, 3 pclkb 2 iclk tmrb 0008 8215h tmr3 time constant register a tcora 8 8 2, 3 pclkb 2 iclk tmrb 0008 8216h tmr2 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk tmrb 0008 8216h tmr23 time constant register b tcorb 16 16 2, 3 pclkb 2 iclk tmrb 0008 8217h tmr3 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk tmrb 0008 8218h tmr2 timer counter tcnt 8 8 2, 3 pclkb 2 iclk tmrb table 4.1 list of i/o register s (address order) (15 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 87 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 8218h tmr23 timer counter tcnt 16 16 2, 3 pclkb 2 iclk tmrb 0008 8219h tmr3 timer counter tcnt 8 8 2, 3 pclkb 2 iclk tmrb 0008 821ah tmr2 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk tmrb 0008 821ah tmr23 timer counter control register tccr 16 16 2, 3 pclkb 2 iclk tmrb 0008 821bh tmr3 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk tmrb 0008 821ch tmr2 time count start register tcstr 8 8 2, 3 pclkb 2 iclk tmrb 0008 821dh tmr3 time count start register tcstr 8 8 2, 3 pclkb 2 iclk tmrb 0008 8280h crc crc control register crccr 8 8 2, 3 pclkb 2 iclk crc 0008 8281h crc crc data input register crcdir 8 8 2, 3 pclkb 2 iclk crc 0008 8282h crc crc data output register crcdor 16 16 2, 3 pclkb 2 iclk crc 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk riica 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk riica 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk riica 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk riica 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk riica 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk riica 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk riica 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk riica 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk riica 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk riica 0008 830ah riic0 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk riica 0008 830bh riic0 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk riica 0008 830ch riic0 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk riica 0008 830dh riic0 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk riica 0008 830eh riic0 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk riica 0008 830fh riic0 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk riica 0008 8310h riic0 i 2 c bus bit rate low register icbrl 8 8 2, 3 pclkb 2 iclk riica 0008 8311h riic0 i 2 c bus bit rate high register icbrh 8 8 2, 3 pclkb 2 iclk riica 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk riica 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk riica 0008 8340h riic2 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk riica 0008 8341h riic2 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk riica 0008 8342h riic2 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk riica 0008 8343h riic2 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk riica 0008 8344h riic2 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk riica 0008 8345h riic2 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk riica 0008 8346h riic2 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk riica 0008 8347h riic2 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk riica 0008 8348h riic2 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk riica 0008 8349h riic2 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk riica 0008 834ah riic2 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk riica 0008 834bh riic2 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk riica 0008 834ch riic2 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk riica 0008 834dh riic2 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk riica 0008 834eh riic2 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk riica 0008 834fh riic2 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk riica 0008 8350h riic2 i 2 c bus bit rate low register icbrl 8 8 2, 3 pclkb 2 iclk riica 0008 8351h riic2 i 2 c bus bit rate high register icbrh 8 8 2, 3 pclkb 2 iclk riica 0008 8352h riic2 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk riica 0008 8353h riic2 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk riica table 4.1 list of i/o register s (address order) (16 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 88 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 8500h mmcif command setting register cecmdset 32 32 2, 3 pclkb 2 iclk mmcif 0008 8508h mmcif argument register cearg 32 32 2, 3 pclkb 2 iclk mmcif 0008 850ch mmcif cmd12 argument register ceargcmd12 32 32 2, 3 pclkb 2 iclk mmcif 0008 8510h mmcif command control register cecmdctrl 32 32 2, 3 pclkb 2 iclk mmcif 0008 8514h mmcif transfer block setting register ceblockset 32 32 2, 3 pclkb 2 iclk mmcif 0008 8518h mmcif clock control register ceclkctrl 32 32 2, 3 pclkb 2 iclk mmcif 0008 851ch mmcif buffer access setting register cebufacc 32 32 2, 3 pclkb 2 iclk mmcif 0008 8520h mmcif response register 3 ceresp3 32 32 2, 3 pclkb 2 iclk mmcif 0008 8524h mmcif response register 2 ceresp2 32 32 2, 3 pclkb 2 iclk mmcif 0008 8528h mmcif response register 1 ceresp1 32 32 2, 3 pclkb 2 iclk mmcif 0008 852ch mmcif response register 0 ceresp0 32 32 2, 3 pclkb 2 iclk mmcif 0008 8530h mmcif cmd12 response register cerespcmd1 2 32 32 2, 3 pclkb 2 iclk mmcif 0008 8534h mmcif data register cedata 32 32 2, 3 pclkb 2 iclk mmcif 0008 853ch mmcif boot operation setting register ceboot 32 32 2, 3 pclkb 2 iclk mmcif 0008 8540h mmcif interrupt status flag register ceint 32 32 2, 3 pclkb 2 iclk mmcif 0008 8544h mmcif interrupt request enable register ceinten 32 32 2, 3 pclkb 2 iclk mmcif 0008 8548h mmcif status register 1 cehoststs1 32 32 2, 3 pclkb 2 iclk mmcif 0008 854ch mmcif status register 2 cehoststs2 32 32 2, 3 pclkb 2 iclk mmcif 0008 8570h mmcif mmc detection and port control register cedetect 32 32 2, 3 pclkb 2 iclk mmcif 0008 8574h mmcif special mode setting register ceaddmode 32 32 2, 3 pclkb 2 iclk mmcif 0008 857ch mmcif version register ceversion 32 32 2, 3 pclkb 2 iclk mmcif 0008 9000h s12ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9004h s12ad a/d channel select register a0 adansa0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9008h s12ad a/d-converted value addition/average mode select register 0 adads0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 900ch s12ad a/d-converted value addition/average count select register adadc 8 8 2, 3 pclkb 2 iclk s12ad c 0008 900eh s12ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9014h s12ad a/d channel select register b0 adansb0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9018h s12ad a/d data duplication register addbldr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9020h s12ad a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9022h s12ad a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9024h s12ad a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9026h s12ad a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9028h s12ad a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk s12ad c 0008 902ah s12ad a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk s12ad c 0008 902ch s12ad a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk s12ad c table 4.1 list of i/o register s (address order) (17 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 89 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 902eh s12ad a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9066h s12ad a/d sample and hold circuit control register adshcr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk s12ad c 0008 907ah s12ad a/d disconnection detection control register addiscr 8 8 2, 3 pclkb 2 iclk s12ad c 0008 907ch s12ad a/d sample-and-hold circuit operating mode select register adshmsr 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9080h s12ad a/d group scan priority control register adgspcr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9084h s12ad a/d data duplication register a addbldra 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9086h s12ad a/d data duplication register b addbldrb 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9090h s12ad a/d compare control register adcmpcr 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9094h s12ad a/d compare channel select register 0 adcmpansr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9098h s12ad a/d compare level register 0 adcmplr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 909ch s12ad a/d compare data register 0 adcmpdr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 909eh s12ad a/d compare data register 1 adcmpdr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 90a0h s12ad a/d compare status register 0 adcmpsr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9100h s12ad1 a/d control register adcsr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9104h s12ad1 a/d channel select register a0 adansa0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9106h s12ad1 a/d channel select register a1 adansa1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9108h s12ad1 a/d-converted value addition/average mode select register 0 adads0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 910ah s12ad1 a/d-converted value addition/average mode select register 1 adads1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 910ch s12ad1 a/d-converted value addition/average count select register adadc 8 8 2, 3 pclkb 2 iclk s12ad c 0008 910eh s12ad1 a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9110h s12ad1 a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9112h s12ad1 a/d conversion extended input control register adexicr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9114h s12ad1 a/d channel select register b0 adansb0 16 16 2, 3 pclkb 2 iclk s12ad c table 4.1 list of i/o register s (address order) (18 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 90 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 9116h s12ad1 a/d channel select register b1 adansb1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9118h s12ad1 a/d data duplication register addbldr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 911ah s12ad1 a/d temperature sensor data register adtsdr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 911ch s12ad1 a/d internal reference voltage data register adocdr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 911eh s12ad1 a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9120h s12ad1 a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9122h s12ad1 a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9124h s12ad1 a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9126h s12ad1 a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9128h s12ad1 a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk s12ad c 0008 912ah s12ad1 a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk s12ad c 0008 912ch s12ad1 a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk s12ad c 0008 912eh s12ad1 a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9130h s12ad1 a/d data register 8 addr8 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9132h s12ad1 a/d data register 9 addr9 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9134h s12ad1 a/d data register 10 addr10 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9136h s12ad1 a/d data register 11 addr11 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9138h s12ad1 a/d data register 12 addr12 16 16 2, 3 pclkb 2 iclk s12ad c 0008 913ah s12ad1 a/d data register 13 addr13 16 16 2, 3 pclkb 2 iclk s12ad c 0008 913ch s12ad1 a/d data register 14 addr14 16 16 2, 3 pclkb 2 iclk s12ad c 0008 913eh s12ad1 a/d data register 15 addr15 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9140h s12ad1 a/d data register 16 addr16 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9142h s12ad1 a/d data register 17 addr17 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9144h s12ad1 a/d data register 18 addr18 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9146h s12ad1 a/d data register 19 addr19 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9148h s12ad1 a/d data register 20 addr20 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9160h s12ad1 a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9161h s12ad1 a/d sampling state register l adsstrl 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9170h s12ad1 a/d sampling state register t adsstrt 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9171h s12ad1 a/d sampling state register o adsstro 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9173h s12ad1 a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk s12ad c table 4.1 list of i/o register s (address order) (19 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 91 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 9174h s12ad1 a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9175h s12ad1 a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9176h s12ad1 a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9177h s12ad1 a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9178h s12ad1 a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9179h s12ad1 a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk s12ad c 0008 917ah s12ad1 a/d disconnection detection control register addiscr 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9180h s12ad1 a/d group scan priority control register adgspcr 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9184h s12ad1 a/d data duplication register a addbldra 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9186h s12ad1 a/d data duplication register b addbldrb 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9190h s12ad1 a/d compare control register adcmpcr 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9192h s12ad1 a/d compare channel select extended register adcmpanser 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9193h s12ad1 a/d compare level extended register adcmpler 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9194h s12ad1 a/d compare channel select register 0 adcmpansr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9196h s12ad1 a/d compare channel select register 1 adcmpansr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 9198h s12ad1 a/d compare level register 0 adcmplr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 919ah s12ad1 a/d compare level register 1 adcmplr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 919ch s12ad1 a/d compare data register 0 adcmpdr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 919eh s12ad1 a/d compare data register 1 adcmpdr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 91a0h s12ad1 a/d compare status register 0 adcmpsr0 16 16 2, 3 pclkb 2 iclk s12ad c 0008 91a2h s12ad1 a/d compare status register 1 adcmpsr1 16 16 2, 3 pclkb 2 iclk s12ad c 0008 91a4h s12ad1 a/d compare status extended register adcmpser 8 8 2, 3 pclkb 2 iclk s12ad c 0008 9e00h qspi qspi control register spcr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e01h qspi qspi slave select polarity register sslp 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e02h qspi qspi pin control register sppcr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e03h qspi qspi status register spsr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e04h qspi qspi data register spdr 32 8, 16, 32 4, 5 pclkb 2, 3 iclk qspi 0008 9e08h qspi qspi sequence control register spscr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e09h qspi qspi sequence status register spssr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e0ah qspi qspi bit rate register spbr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e0bh qspi qspi data control register spdcr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e0ch qspi qspi clock delay register spckd 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e0dh qspi qspi slave select negation delay register sslnd 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e0eh qspi qspi next-access delay register spnd 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e10h qspi qspi command register 0 spcmd0 16 16 4, 5 pclkb 2, 3 iclk qspi 0008 9e12h qspi qspi command register 1 spcmd1 16 16 4, 5 pclkb 2, 3 iclk qspi 0008 9e14h qspi qspi command register 2 spcmd2 16 16 4, 5 pclkb 2, 3 iclk qspi table 4.1 list of i/o register s (address order) (20 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 92 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 9e16h qspi qspi command register 3 spcmd3 16 16 4, 5 pclkb 2, 3 iclk qspi 0008 9e18h qspi qspi buffer control register spbfcr 8 8 4, 5 pclkb 2, 3 iclk qspi 0008 9e1ah qspi qspi buffer data count register spbdcr 16 16 4, 5 pclkb 2, 3 iclk qspi 0008 9e1ch qspi qspi transfer data length multiplier setting register 0 spbmul0 32 32 4, 5 pclkb 2, 3 iclk qspi 0008 9e20h qspi qspi transfer data length multiplier setting register 1 spbmul1 32 32 4, 5 pclkb 2, 3 iclk qspi 0008 9e24h qspi qspi transfer data length multiplier setting register 2 spbmul2 32 32 4, 5 pclkb 2, 3 iclk qspi 0008 9e28h qspi qspi transfer data length multiplier setting register 3 spbmul3 32 32 4, 5 pclkb 2, 3 iclk qspi 0008 a000h sci0 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a001h sci0 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a002h sci0 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a003h sci0 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a004h sci0 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a005h sci0 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a006h sci0 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a007h sci0 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a008h sci0 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00ch sci0 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00dh sci0 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00eh sci0 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00fh sci0 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a00eh sci0 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a010h sci0 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a011h sci0 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a010h sci0 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a012h sci0 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a020h sci1 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a021h sci1 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a022h sci1 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a023h sci1 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a024h sci1 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih table 4.1 list of i/o register s (address order) (21 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 93 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 a025h sci1 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a026h sci1 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a027h sci1 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a028h sci1 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02ch sci1 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02dh sci1 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02eh sci1 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02fh sci1 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a02eh sci1 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a030h sci1 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a031h sci1 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a030h sci1 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a032h sci1 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a040h sci2 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a041h sci2 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a042h sci2 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a043h sci2 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a044h sci2 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a045h sci2 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a046h sci2 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a047h sci2 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a048h sci2 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a049h sci2 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04ah sci2 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04bh sci2 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04ch sci2 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04dh sci2 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04eh sci2 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih table 4.1 list of i/o register s (address order) (22 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 94 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 a04fh sci2 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a04eh sci2 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a050h sci2 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a051h sci2 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a050h sci2 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a052h sci2 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a060h sci3 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a061h sci3 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a062h sci3 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a063h sci3 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a064h sci3 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a065h sci3 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a066h sci3 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a067h sci3 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a068h sci3 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a069h sci3 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06ah sci3 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06bh sci3 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06ch sci3 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06dh sci3 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06eh sci3 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06fh sci3 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a06eh sci3 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a070h sci3 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a071h sci3 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a070h sci3 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a072h sci3 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a080h sci4 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a081h sci4 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a082h sci4 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a083h sci4 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih table 4.1 list of i/o register s (address order) (23 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 95 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 a084h sci4 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a085h sci4 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a086h sci4 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a087h sci4 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a088h sci4 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a089h sci4 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08ah sci4 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08bh sci4 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08ch sci4 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08dh sci4 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08eh sci4 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08fh sci4 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a08eh sci4 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a090h sci4 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a091h sci4 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a090h sci4 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a092h sci4 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a0h sci5 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a1h sci5 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a2h sci5 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a3h sci5 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a4h sci5 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a5h sci5 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a6h sci5 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a7h sci5 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a8h sci5 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0ach sci5 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0adh sci5 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih table 4.1 list of i/o register s (address order) (24 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 96 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 a0aeh sci5 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0afh sci5 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0aeh sci5 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0b0h sci5 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0b1h sci5 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0b0h sci5 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0b2h sci5 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c0h sci6 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c1h sci6 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c2h sci6 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c3h sci6 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c4h sci6 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c5h sci6 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c6h sci6 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c7h sci6 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c8h sci6 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0cch sci6 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0cdh sci6 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0ceh sci6 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0cfh sci6 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0ceh sci6 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0d0h sci6 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0d1h sci6 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0d0h sci6 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0d2h sci6 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e0h sci7 serial mode register smr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e1h sci7 bit rate register brr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e2h sci7 serial control register scr 8 8 2, 3 pclkb 2 iclk scig, scih table 4.1 list of i/o register s (address order) (25 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 97 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 a0e3h sci7 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e4h sci7 serial status register ssr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e5h sci7 receive data register rdr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e6h sci7 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e7h sci7 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e8h sci7 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0e9h sci7 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0eah sci7 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0ebh sci7 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0ech sci7 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0edh sci7 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0eeh sci7 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0efh sci7 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0eeh sci7 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0f0h sci7 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0f1h sci7 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a0f0h sci7 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 a0f2h sci7 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scig, scih 0008 a500h ssi0 control register ssicr 32 32 2, 3 pclkb 2 iclk ssi 0008 a504h ssi0 status register ssisr 32 32 2, 3 pclkb 2 iclk ssi 0008 a510h ssi0 fifo control register ssifcr 32 32 2, 3 pclkb 2 iclk ssi 0008 a514h ssi0 fifo status register ssifsr 32 32 2, 3 pclkb 2 iclk ssi 0008 a518h ssi0 transmit fifo data register ssiftdr 32 32 2, 3 pclkb 2 iclk ssi 0008 a51ch ssi0 receive fifo data register ssifrdr 32 32 2, 3 pclkb 2 iclk ssi 0008 a520h ssi0 tdm mode register ssitdmr 32 32 2, 3 pclkb 2 iclk ssi 0008 a540h ssi1 control register ssicr 32 32 2, 3 pclkb 2 iclk ssi 0008 a544h ssi1 status register ssisr 32 32 2, 3 pclkb 2 iclk ssi 0008 a550h ssi1 fifo control register ssifcr 32 32 2, 3 pclkb 2 iclk ssi 0008 a554h ssi1 fifo status register ssifsr 32 32 2, 3 pclkb 2 iclk ssi 0008 a558h ssi1 transmit fifo data register ssiftdr 32 32 2, 3 pclkb 2 iclk ssi 0008 a55ch ssi1 receive fifo data register ssifrdr 32 32 2, 3 pclkb 2 iclk ssi 0008 a560h ssi1 tdm mode register ssitdmr 32 32 2, 3 pclkb 2 iclk ssi 0008 ac00h sdhi command register sdcmd 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac08h sdhi argument register sdarg 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac10h sdhi data stop register sdstop 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac14h sdhi block count register sdblkcnt 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac18h sdhi response register 10 sdrsp10 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac20h sdhi response register 32 sdrsp32 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac28h sdhi response register 54 sdrsp54 32 32 2 to 3 pclkb 2 iclk sdhi table 4.1 list of i/o register s (address order) (26 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 98 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 ac30h sdhi response register 76 sdrsp76 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac38h sdhi sd status register 1 sdsts1 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac3ch sdhi sd status register 2 sdsts2 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac40h sdhi sd interrupt mask register 1 sdimsk1 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac44h sdhi sd interrupt mask register 2 sdimsk2 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac48h sdhi sdhi clock control register sdclkcr 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac4ch sdhi transfer data size register sdsize 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac50h sdhi card access option register sdopt 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac58h sdhi sd error status register 1 sdersts1 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac5ch sdhi sd error status register 2 sdersts2 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac60h sdhi sd buffer register sdbufr 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac68h sdhi sdio mode control register sdiomd 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac6ch sdhi sdio status register sdiosts 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ac70h sdhi sdio interrupt mask register sdioimsk 32 32 2 to 3 pclkb 2 iclk sdhi 0008 adb0h sdhi dma transfer enable register sddmaen 32 32 2 to 3 pclkb 2 iclk sdhi 0008 adc0h sdhi sdhi software reset register sdrst 32 32 2 to 3 pclkb 2 iclk sdhi 0008 adc4h sdhi version register sdver 32 32 2 to 3 pclkb 2 iclk sdhi 0008 ade0h sdhi swap control register sdswap 32 32 2 to 3 pclkb 2 iclk sdhi 0008 b000h cac cac control register 0 cacr0 8 8 2, 3 pclkb 2 iclk cac 0008 b001h cac cac control register 1 cacr1 8 8 2, 3 pclkb 2 iclk cac 0008 b002h cac cac control register 2 cacr2 8 8 2, 3 pclkb 2 iclk cac 0008 b003h cac cac interrupt request enable register caicr 8 8 2, 3 pclkb 2 iclk cac 0008 b004h cac cac status register castr 8 8 2, 3 pclkb 2 iclk cac 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2, 3 pclkb 2 iclk cac 0008 b008h cac cac lower-limit value setting register callvr 16 16 2, 3 pclkb 2 iclk cac 0008 b00ah cac cac counter buffer register cacntbr 16 16 2, 3 pclkb 2 iclk cac 0008 b080h doc doc control register docr 8 8 2, 3 pclkb 2 iclk doc 0008 b082h doc doc data input register dodir 16 16 2, 3 pclkb 2 iclk doc 0008 b084h doc doc data setting register dodsr 16 16 2, 3 pclkb 2 iclk doc 0008 b100h elc event link control register elcr 8 8 2, 3 pclkb 2 iclk elc 0008 b101h elc event link setting register 0 elsr0 8 8 2, 3 pclkb 2 iclk elc 0008 b104h elc event link setting register 3 elsr3 8 8 2, 3 pclkb 2 iclk elc 0008 b105h elc event link setting register 4 elsr4 8 8 2, 3 pclkb 2 iclk elc 0008 b108h elc event link setting register 7 elsr7 8 8 2, 3 pclkb 2 iclk elc 0008 b10bh elc event link setting register 10 elsr10 8 8 2, 3 pclkb 2 iclk elc 0008 b10ch elc event link setting register 11 elsr11 8 8 2, 3 pclkb 2 iclk elc 0008 b10dh elc event link setting register 12 elsr12 8 8 2, 3 pclkb 2 iclk elc 0008 b10eh elc event link setting register 13 elsr13 8 8 2, 3 pclkb 2 iclk elc 0008 b110h elc event link setting register 15 elsr15 8 8 2, 3 pclkb 2 iclk elc 0008 b111h elc event link setting register 16 elsr16 8 8 2, 3 pclkb 2 iclk elc 0008 b113h elc event link setting register 18 elsr18 8 8 2, 3 pclkb 2 iclk elc 0008 b114h elc event link setting register 19 elsr19 8 8 2, 3 pclkb 2 iclk elc 0008 b115h elc event link setting register 20 elsr20 8 8 2, 3 pclkb 2 iclk elc 0008 b116h elc event link setting register 21 elsr21 8 8 2, 3 pclkb 2 iclk elc 0008 b117h elc event link setting register 22 elsr22 8 8 2, 3 pclkb 2 iclk elc 0008 b118h elc event link setting register 23 elsr23 8 8 2, 3 pclkb 2 iclk elc 0008 b119h elc event link setting register 24 elsr24 8 8 2, 3 pclkb 2 iclk elc 0008 b11ah elc event link setting register 25 elsr25 8 8 2, 3 pclkb 2 iclk elc 0008 b11bh elc event link setting register 26 elsr26 8 8 2, 3 pclkb 2 iclk elc 0008 b11ch elc event link setting register 27 elsr27 8 8 2, 3 pclkb 2 iclk elc table 4.1 list of i/o register s (address order) (27 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 99 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 b11dh elc event link setting register 28 elsr28 8 8 2, 3 pclkb 2 iclk elc 0008 b11fh elc event link option setting register a elopa 8 8 2, 3 pclkb 2 iclk elc 0008 b120h elc event link option setting register b elopb 8 8 2, 3 pclkb 2 iclk elc 0008 b121h elc event link option setting register c elopc 8 8 2, 3 pclkb 2 iclk elc 0008 b122h elc event link option setting register d elopd 8 8 2, 3 pclkb 2 iclk elc 0008 b123h elc port group setting register 1 pgr1 8 8 2, 3 pclkb 2 iclk elc 0008 b124h elc port group setting register 2 pgr2 8 8 2, 3 pclkb 2 iclk elc 0008 b125h elc port group control register 1 pgc1 8 8 2, 3 pclkb 2 iclk elc 0008 b126h elc port group control register 2 pgc2 8 8 2, 3 pclkb 2 iclk elc 0008 b127h elc port buffer register 1 pdbf1 8 8 2, 3 pclkb 2 iclk elc 0008 b128h elc port buffer register 2 pdbf2 8 8 2, 3 pclkb 2 iclk elc 0008 b129h elc event link port setting register 0 pel0 8 8 2, 3 pclkb 2 iclk elc 0008 b12ah elc event link port setting register 1 pel1 8 8 2, 3 pclkb 2 iclk elc 0008 b12bh elc event link port setting register 2 pel2 8 8 2, 3 pclkb 2 iclk elc 0008 b12ch elc event link port setting register 3 pel3 8 8 2, 3 pclkb 2 iclk elc 0008 b12dh elc event link software event generation register elsegr 8 8 2, 3 pclkb 2 iclk elc 0008 b131h elc event link setting register 33 elsr33 8 8 2, 3 pclkb 2 iclk elc 0008 b133h elc event link setting register 35 elsr35 8 8 2, 3 pclkb 2 iclk elc 0008 b134h elc event link setting register 36 elsr36 8 8 2, 3 pclkb 2 iclk elc 0008 b135h elc event link setting register 37 elsr37 8 8 2, 3 pclkb 2 iclk elc 0008 b136h elc event link setting register 38 elsr38 8 8 2, 3 pclkb 2 iclk elc 0008 b139h elc event link setting register 41 elsr41 8 8 2, 3 pclkb 2 iclk elc 0008 b13ah elc event link setting register 42 elsr42 8 8 2, 3 pclkb 2 iclk elc 0008 b13bh elc event link setting register 43 elsr43 8 8 2, 3 pclkb 2 iclk elc 0008 b13ch elc event link setting register 44 elsr44 8 8 2, 3 pclkb 2 iclk elc 0008 b13dh elc event link setting register 45 elsr45 8 8 2, 3 pclkb 2 iclk elc 0008 b13fh elc event link option setting register f elopf 8 8 2, 3 pclkb 2 iclk elc 0008 b141h elc event link option setting register h eloph 8 8 2, 3 pclkb 2 iclk elc 0008 b142h elc event link option setting register i elopi 8 8 2, 3 pclkb 2 iclk elc 0008 b143h elc event link option setting register j elopj 8 8 2, 3 pclkb 2 iclk elc 0008 b300h sci12 serial mode register smr 8 8 2, 3 pclkb 2 iclk scih 0008 b301h sci12 bit rate register brr 8 8 2, 3 pclkb 2 iclk scih 0008 b302h sci12 serial control register scr 8 8 2, 3 pclkb 2 iclk scih 0008 b303h sci12 transmit data register tdr 8 8 2, 3 pclkb 2 iclk scih 0008 b304h sci12 serial status register ssr 8 8 2, 3 pclkb 2 iclk scih 0008 b305h sci12 receive data register rdr 8 8 2, 3 pclkb 2 iclk scih 0008 b306h sci12 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk scih 0008 b307h sci12 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk scih 0008 b308h sci12 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scih 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk scih 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk scih 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk scih 0008 b30ch sci12 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk scih 0008 b30dh sci12 spi mode register spmr 8 8 2, 3 pclkb 2 iclk scih 0008 b30eh sci12 transmit data register h tdrh 8 8 2, 3 pclkb 2 iclk scih 0008 b30fh sci12 transmit data register l tdrl 8 8 2, 3 pclkb 2 iclk scih 0008 b30eh sci12 transmit data register hl tdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 b310h sci12 receive data register h rdrh 8 8 2, 3 pclkb 2 iclk scih 0008 b311h sci12 receive data register l rdrl 8 8 2, 3 pclkb 2 iclk scih table 4.1 list of i/o register s (address order) (28 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 100 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 b310h sci12 receive data register hl rdrhl 16 16 4, 5 pclkb 2 iclk scig, scih 0008 b312h sci12 modulation duty register mddr 8 8 2, 3 pclkb 2 iclk scih 0008 b320h sci12 extended serial module enable register esmer 8 8 2, 3 pclkb 2 iclk scih 0008 b321h sci12 control register 0 cr0 8 8 2, 3 pclkb 2 iclk scih 0008 b322h sci12 control register 1 cr1 8 8 2, 3 pclkb 2 iclk scih 0008 b323h sci12 control register 2 cr2 8 8 2, 3 pclkb 2 iclk scih 0008 b324h sci12 control register 3 cr3 8 8 2, 3 pclkb 2 iclk scih 0008 b325h sci12 port control register pcr 8 8 2, 3 pclkb 2 iclk scih 0008 b326h sci12 interrupt control register icr 8 8 2, 3 pclkb 2 iclk scih 0008 b327h sci12 status register str 8 8 2, 3 pclkb 2 iclk scih 0008 b328h sci12 status clear register stcr 8 8 2, 3 pclkb 2 iclk scih 0008 b329h sci12 control field 0 data register cf0dr 8 8 2, 3 pclkb 2 iclk scih 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2, 3 pclkb 2 iclk scih 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2, 3 pclkb 2 iclk scih 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2, 3 pclkb 2 iclk scih 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2, 3 pclkb 2 iclk scih 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2, 3 pclkb 2 iclk scih 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2, 3 pclkb 2 iclk scih 0008 b330h sci12 timer control register tcr 8 8 2, 3 pclkb 2 iclk scih 0008 b331h sci12 timer mode register tmr 8 8 2, 3 pclkb 2 iclk scih 0008 b332h sci12 timer prescaler register tpre 8 8 2, 3 pclkb 2 iclk scih 0008 b333h sci12 timer count register tcnt 8 8 2, 3 pclkb 2 iclk scih 0008 c000h port0 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c001h port1 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c002h port2 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c003h port3 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c004h port4 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c005h port5 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c006h port6 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c007h port7 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c008h port8 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c009h port9 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00ah porta port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00bh portb port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00ch portc port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00dh portd port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00eh porte port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c00fh portf port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c010h portg port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports table 4.1 list of i/o register s (address order) (29 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 101 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c012h portj port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c020h port0 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c021h port1 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c022h port2 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c023h port3 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c024h port4 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c025h port5 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c026h port6 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c027h port7 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c028h port8 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c029h port9 port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02ah porta port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02bh portb port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02ch portc port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02dh portd port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02eh porte port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02fh portf port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c030h portg port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c032h portj port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c040h port0 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c041h port1 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c042h port2 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c043h port3 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c044h port4 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c045h port5 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c046h port6 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c047h port7 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c048h port8 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c049h port9 port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c04ah porta port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c04bh portb port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports table 4.1 list of i/o register s (address order) (30 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 102 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c04ch portc port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c04dh portd port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c04eh porte port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c04fh portf port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c050h portg port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c052h portj port input register pidr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c060h port0 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c061h port1 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c062h port2 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c063h port3 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c064h port4 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c065h port5 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c066h port6 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c067h port7 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c068h port8 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c069h port9 port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06ah porta port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06bh portb port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06ch portc port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06dh portd port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06eh porte port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c06fh portf port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c070h portg port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c072h portj port mode register pmr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c080h port0 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c081h port0 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c082h port1 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c083h port1 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c084h port2 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c085h port2 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c086h port3 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports table 4.1 list of i/o register s (address order) (31 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 103 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c087h port3 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c088h port4 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c089h port4 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08ah port5 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08bh port5 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08ch port6 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08dh port6 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08eh port7 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c08fh port7 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c090h port8 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c091h port8 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c092h port9 open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c093h port9 open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c094h porta open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c095h porta open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c096h portb open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c097h portb open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c098h portc open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c099h portc open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09ah portd open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09bh portd open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09ch porte open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09dh porte open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09eh portf open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c09fh portf open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0a0h portg open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0a1h portg open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0a4h portj open-drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0a5h portj open-drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c0h port0 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c1h port1 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports table 4.1 list of i/o register s (address order) (32 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 104 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c0c2h port2 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c3h port3 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c4h port4 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c5h port5 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c6h port6 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c7h port7 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c8h port8 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0c9h port9 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0cah porta pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0cbh portb pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0cch portc pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0cdh portd pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0ceh porte pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0cfh portf pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0d0h portg pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0d2h portj pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0e0h port0 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0e2h port2 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0e5h port5 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0e9h port9 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0eah porta drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0ebh portb drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0ech portc drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0edh portd drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0eeh porte drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c0f0h portg drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c100h mpc cs output enable register pfcse 8 8 2, 3 pclkb 2 iclk mpc 0008 c102h mpc cs output pin select register 0 pfcss0 8 8 2, 3 pclkb 2 iclk mpc 0008 c103h mpc cs output pin select register 1 pfcss1 8 8 2, 3 pclkb 2 iclk mpc 0008 c104h mpc address output enable register 0 pfaoe0 8 8 2, 3 pclkb 2 iclk mpc 0008 c105h mpc address output enable register 1 pfaoe1 8 8 2, 3 pclkb 2 iclk mpc 0008 c106h mpc external bus control register 0 pfbcr0 8 8 2, 3 pclkb 2 iclk mpc 0008 c107h mpc external bus control register 1 pfbcr1 8 8 2, 3 pclkb 2 iclk mpc 0008 c10eh mpc ethernet control register pfenet 8 8 2, 3 pclkb 2 iclk mpc 0008 c11fh mpc write-protect register pwpr 8 8 2, 3 pclkb 2 iclk mpc table 4.1 list of i/o register s (address order) (33 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 105 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c140h mpc p00 pin function control register p00pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c141h mpc p01 pin function control register p01pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c142h mpc p02 pin function control register p02pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c143h mpc p03 pin function control register p03pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c145h mpc p05 pin function control register p05pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c147h mpc p07 pin function control register p07pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c148h mpc p10 pin function control register p10pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c149h mpc p11 pin function control register p11pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c150h mpc p20 pin function control register p20pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c151h mpc p21 pin function control register p21pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c152h mpc p22 pin function control register p22pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c153h mpc p23 pin function control register p23pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c154h mpc p24 pin function control register p24pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c155h mpc p25 pin function control register p25pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c156h mpc p26 pin function control register p26pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c157h mpc p27 pin function control register p27pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c158h mpc p30 pin function control register p30pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c159h mpc p31 pin function control register p31pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c160h mpc p40 pin function control register p40pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c161h mpc p41 pin function control register p41pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c162h mpc p42 pin function control register p42pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c163h mpc p43 pin function control register p43pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c164h mpc p44 pin function control register p44pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c165h mpc p45 pin function control register p45pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c166h mpc p46 pin function control register p46pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c167h mpc p47 pin function control register p47pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c168h mpc p50 pin function control register p50pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c169h mpc p51 pin function control register p51pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c16eh mpc p56 pin function control register p56pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c170h mpc p60 pin function control register p60pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c176h mpc p66 pin function control register p66pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c177h mpc p67 pin function control register p67pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c179h mpc p71 pin function control register p71pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c17ah mpc p72 pin function control register p72pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c17bh mpc p73 pin function control register p73pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c17ch mpc p74 pin function control register p74pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c17dh mpc p75 pin function control register p75pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c17eh mpc p76 pin function control register p76pfs 8 8 2, 3 pclkb 2 iclk mpc table 4.1 list of i/o register s (address order) (34 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 106 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c17fh mpc p77 pin function control register p77pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c180h mpc p80 pin function control register p80pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c181h mpc p81 pin function control register p81pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c182h mpc p82 pin function control register p82pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c183h mpc p83 pin function control register p83pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c186h mpc p86 pin function control register p86pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c187h mpc p87 pin function control register p87pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c188h mpc p90 pin function control register p90pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c189h mpc p91 pin function control register p91pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18bh mpc p93 pin function control register p93pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18ch mpc p94 pin function control register p94pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18dh mpc p95 pin function control register p95pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18eh mpc p96 pin function control register p96pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c18fh mpc p97 pin function control register p97pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c197h mpc pa7 pin function control register pa7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2, 3 pclkb 2 iclk mpc table 4.1 list of i/o register s (address order) (35 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 107 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b6h mpc pe6 pin function control register pe6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b7h mpc pe7 pin function control register pe7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b8h mpc pf0 pin function control register pf0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1b9h mpc pf1 pin function control register pf1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1bah mpc pf2 pin function control register pf2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1bdh mpc pf5 pin function control register pf5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c0h mpc pg0 pin function control register pg0pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c1h mpc pg1 pin function control register pg1pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c2h mpc pg2 pin function control register pg2pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c3h mpc pg3 pin function control register pg3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c4h mpc pg4 pin function control register pg4pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c5h mpc pg5 pin function control register pg5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c6h mpc pg6 pin function control register pg6pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1c7h mpc pg7 pin function control register pg7pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1d3h mpc pj3 pin function control register pj3pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c1d5h mpc pj5 pin function control register pj5pfs 8 8 2, 3 pclkb 2 iclk mpc 0008 c280h syste m deep standby control register dpsbycr 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c282h syste m deep standby interrupt enable register 0 dpsier0 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c283h syste m deep standby interrupt enable register 1 dpsier1 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c284h syste m deep standby interrupt enable register 2 dpsier2 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c285h syste m deep standby interrupt enable register 3 dpsier3 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c286h syste m deep standby interrupt flag register 0 dpsifr0 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c287h syste m deep standby interrupt flag register 1 dpsifr1 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c288h syste m deep standby interrupt flag register 2 dpsifr2 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c289h syste m deep standby interrupt flag register 3 dpsifr3 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c28ah syste m deep standby interrupt edge register 0 dpsiegr0 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c28bh syste m deep standby interrupt edge register 1 dpsiegr1 8 8 4, 5 pclkb 2, 3 iclk low power consum ption table 4.1 list of i/o register s (address order) (36 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 108 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c28ch syste m deep standby interrupt edge register 2 dpsiegr2 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c28dh syste m deep standby interrupt edge register 3 dpsiegr3 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c290h syste m reset status register 0 rstsr0 8 8 4, 5 pclkb 2, 3 iclk resets 0008 c291h syste m reset status register 1 rstsr1 8 8 4, 5 pclkb 2, 3 iclk resets 0008 c293h syste m main clock oscillator forced oscillation control register mofcr 8 8 4, 5 pclkb 2, 3 iclk clock generat ion circuit 0008 c294h syste m high-speed on-chip oscillator power supply control register hocopcr 8 8 4, 5 pclkb 2, 3 iclk clock generat ion circuit 0008 c297h syste m voltage monitoring circuit control register lvcmpcr 8 8 4, 5 pclkb 2, 3 iclk ldva 0008 c298h syste m voltage detection level select register lvdlvlr 8 8 4, 5 pclkb 2, 3 iclk ldva 0008 c29ah syste m voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4, 5 pclkb 2, 3 iclk ldva 0008 c29bh syste m voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4, 5 pclkb 2, 3 iclk ldva 0008 c2a0h to 0008 c2bfh syste m deep standby backup registers 0 to 31 dpsbkr0 to 31 8 8 4, 5 pclkb 2, 3 iclk low power consum ption 0008 c400h rtc 64-hz counter r64cnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c402h rtc second counter rseccnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c402h rtc binary counter 0 bcnt0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c404h rtc minute counter rmincnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c404h rtc binary counter 1 bcnt1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c406h rtc hour counter rhrcnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c406h rtc binary counter 2 bcnt2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c408h rtc day-of-week counter rwkcnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c408h rtc binary counter 3 bcnt3 8 8 2, 3 pclkb 2 iclk rtcd 0008 c40ah rtc date counter rdaycnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c40ch rtc month counter rmoncnt 8 8 2, 3 pclkb 2 iclk rtcd 0008 c40eh rtc year counter ryrcnt 16 16 2, 3 pclkb 2 iclk rtcd 0008 c410h rtc second alarm register rsecar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c410h rtc binary counter 0 alarm register bcnt0ar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c412h rtc minute alarm register rminar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c412h rtc binary counter 1 alarm register bcnt1ar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c414h rtc hour alarm register rhrar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c414h rtc binary counter 2 alarm register bcnt2ar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c416h rtc day-of-week alarm register rwkar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c416h rtc binary counter 3 alarm register bcnt3ar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c418h rtc date alarm register rdayar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c418h rtc binary counter 0 alarm enable register bcnt0aer 8 8 2, 3 pclkb 2 iclk rtcd 0008 c41ah rtc month alarm register rmonar 8 8 2, 3 pclkb 2 iclk rtcd 0008 c41ah rtc binary counter 1 alarm enable register bcnt1aer 8 8 2, 3 pclkb 2 iclk rtcd 0008 c41ch rtc year alarm register ryrar 16 16 2, 3 pclkb 2 iclk rtcd 0008 c41ch rtc binary counter 2 alarm enable register bcnt2aer 16 16 2, 3 pclkb 2 iclk rtcd 0008 c41eh rtc year alarm enable register ryraren 8 8 2, 3 pclkb 2 iclk rtcd table 4.1 list of i/o register s (address order) (37 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 109 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c41eh rtc binary counter 3 alarm enable register bcnt3aer 8 8 2, 3 pclkb 2 iclk rtcd 0008 c422h rtc rtc control register 1 rcr1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c424h rtc rtc control register 2 rcr2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c426h rtc rtc control register 3 rcr3 8 8 2, 3 pclkb 2 iclk rtcd 0008 c428h rtc rtc control register 4 rcr4 8 8 2, 3 pclkb 2 iclk rtcd 0008 c42ah rtc frequency register h rfrh 16 16 2, 3 pclkb 2 iclk rtcd 0008 c42ch rtc frequency register l rfrl 16 16 2, 3 pclkb 2 iclk rtcd 0008 c42eh rtc time error adjustment register radj 8 8 2, 3 pclkb 2 iclk rtcd 0008 c440h rtc time capture control register 0 rtccr0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c442h rtc time capture control register 1 rtccr1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c444h rtc time capture control register 2 rtccr2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c452h rtc second capture register 0 rseccp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c452h rtc bcnt0 capture register 0 bcnt0cp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c454h rtc minute capture register 0 rmincp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c454h rtc bcnt1 capture register 0 bcnt1cp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c456h rtc hour capture register 0 rhrcp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c456h rtc bcnt2 capture register 0 bcnt2cp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c45ah rtc date capture register 0 rdaycp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c45ah rtc bcnt3 capture register 0 bcnt3cp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c45ch rtc month capture register 0 rmoncp0 8 8 2, 3 pclkb 2 iclk rtcd 0008 c462h rtc second capture register 1 rseccp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c462h rtc bcnt0 capture register 1 bcnt0cp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c464h rtc minute capture register 1 rmincp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c464h rtc bcnt1 capture register 1 bcnt1cp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c466h rtc hour capture register 1 rhrcp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c466h rtc bcnt2 capture register 1 bcnt2cp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c46ah rtc date capture register 1 rdaycp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c46ah rtc bcnt3 capture register 1 bcnt3cp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c46ch rtc month capture register 1 rmoncp1 8 8 2, 3 pclkb 2 iclk rtcd 0008 c472h rtc second capture register 2 rseccp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c472h rtc bcnt0 capture register 2 bcnt0cp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c474h rtc minute capture register 2 rmincp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c474h rtc bcnt1 capture register 2 bcnt1cp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c476h rtc hour capture register 2 rhrcp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c476h rtc bcnt2 capture register 2 bcnt2cp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c47ah rtc date capture register 2 rdaycp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c47ah rtc bcnt3 capture register 2 bcnt3cp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c47ch rtc month capture register 2 rmoncp2 8 8 2, 3 pclkb 2 iclk rtcd 0008 c4c0h poe3 input level control/status register 1 icsr1 16 16 2, 3 pclkb 2 iclk poe3 0008 c4c2h poe3 output level control/status register 1 ocsr1 16 16 2, 3 pclkb 2 iclk poe3 0008 c4c4h poe3 input level control/status register 2 icsr2 16 16 2, 3 pclkb 2 iclk poe3 0008 c4c6h poe3 output level control/status register 2 ocsr2 16 16 2, 3 pclkb 2 iclk poe3 0008 c4c8h poe3 input level control/status register 3 icsr3 16 16 2, 3 pclkb 2 iclk poe3 0008 c4cah poe3 software port output enable register spoer 8 8 2, 3 pclkb 2 iclk poe3 0008 c4cbh poe3 port output enable control register 1 poecr1 8 8 2, 3 pclkb 2 iclk poe3 0008 c4cch poe3 port output enable control register 2 poecr2 16 16 2, 3 pclkb 2 iclk poe3 0008 c4ceh poe3 port output enable control register 3 poecr3 16 16 2, 3 pclkb 2 iclk poe3 0008 c4d0h poe3 port output enable control register 4 poecr4 16 16 2, 3 pclkb 2 iclk poe3 0008 c4d2h poe3 port output enable control register 5 poecr5 16 16 2, 3 pclkb 2 iclk poe3 0008 c4d4h poe3 port output enable control register 6 poecr6 16 16 2, 3 pclkb 2 iclk poe3 table 4.1 list of i/o register s (address order) (38 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 110 of 230 jul 31, 2014 rx64m group 4. i/o registers 0008 c4d6h poe3 input level control/status register 4 icsr4 16 16 2, 3 pclkb 2 iclk poe3 0008 c4d8h poe3 input level control/status register 5 icsr5 16 16 2, 3 pclkb 2 iclk poe3 0008 c4dah poe3 active level setting register 1 alr1 16 16 2, 3 pclkb 2 iclk poe3 0008 c4dch poe3 input level control/status register 6 icsr6 16 16 2, 3 pclkb 2 iclk poe3 0008 c4e0h poe3 gpt0 pin select register g0selr 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e1h poe3 gpt1 pin select register g1selr 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e2h poe3 gpt2 pin select register g2selr 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e3h poe3 gpt3 pin select register g3selr 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e4h poe3 mtu0 pin select register 1 m0selr1 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e5h poe3 mtu0 pin select register 2 m0selr2 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e6h poe3 mtu3 pin select register m3selr 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e7h poe3 mtu4 pin select register 1 m4selr1 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e8h poe3 mtu4 pin select register 2 m4selr2 8 8 2, 3 pclkb 2 iclk poe3 0008 c4e9h poe3 mtu/gpt pin select register mgselr 8 8 2, 3 pclkb 2 iclk poe3 0008 c500h temps temperature sensor control register tscr 8 8 2, 3 pclkb 2 iclk temps 0008 c5c0h da d/a a/d synchronous unit select register daadusr 8 8 2, 3 pclkb 2 iclk r12da 0009 0200h to 0009 03ffh can0 mailbox registers 0 to 31 mb0 to 31 128 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0400h to 0009 041fh can0 mask registers 0 to 7 mkr0 to 7 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0420h can0 fifo received id compare register 0 fidcr0 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0424h can0 fifo received id compare register 1 fidcr1 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0428h can0 mask invalid register mkivlr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 042ch can0 mailbox interrupt enable register mier 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0820h to 0009 083fh can0 message control registers 0 to 31 mctl0 to 31 8 8 2, 3 pclkb 2 iclk can 0009 0840h can0 control register ctlr 16 8, 16 2, 3 pclkb 2 iclk can 0009 0842h can0 status register str 16 8, 16 2, 3 pclkb 2 iclk can 0009 0844h can0 bit configuration register bcr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 0848h can0 receive fifo control register rfcr 8 8 2, 3 pclkb 2 iclk can 0009 0849h can0 receive fifo pointer control register rfpcr 8 8 2, 3 pclkb 2 iclk can 0009 084ah can0 transmit fifo control register tfcr 8 8 2, 3 pclkb 2 iclk can 0009 084bh can0 transmit fifo pointer control register tfpcr 8 8 2, 3 pclkb 2 iclk can 0009 084ch can0 error interrupt enable register eier 8 8 2, 3 pclkb 2 iclk can 0009 084dh can0 error interrupt factor judge register eifr 8 8 2, 3 pclkb 2 iclk can 0009 084eh can0 receive error count register recr 8 8 2, 3 pclkb 2 iclk can 0009 084fh can0 transmit error count register tecr 8 8 2, 3 pclkb 2 iclk can 0009 0850h can0 error code store register ecsr 8 8 2, 3 pclkb 2 iclk can 0009 0851h can0 channel search support register cssr 8 8 2, 3 pclkb 2 iclk can 0009 0852h can0 mailbox search status register mssr 8 8 2, 3 pclkb 2 iclk can 0009 0853h can0 mailbox search mode register msmr 8 8 2, 3 pclkb 2 iclk can 0009 0854h can0 time stamp register tsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 0856h can0 acceptance filter support register afsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 0858h can0 test control register tcr 8 8 2, 3 pclkb 2 iclk can 0009 1200h to 0009 13ffh can1 mailbox registers 0 to 31 mb0 to 31 128 8, 16, 32 2, 3 pclkb 2 iclk can 0009 1400h to 0009 141fh can1 mask registers 0 to 7 mkr0 to 7 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 1420h can1 fifo received id compare register 0 fidcr0 32 8, 16, 32 2, 3 pclkb 2 iclk can table 4.1 list of i/o register s (address order) (39 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 111 of 230 jul 31, 2014 rx64m group 4. i/o registers 0009 1424h can1 fifo received id compare register 1 fidcr1 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 1428h can1 mask invalid register mkivlr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 142ch can1 mailbox interrupt enable register mier 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 1820h to 0009 183fh can1 message control registers 0 to 31 mctl0 to 31 8 8 2, 3 pclkb 2 iclk can 0009 1840h can1 control register ctlr 16 8, 16 2, 3 pclkb 2 iclk can 0009 1842h can1 status register str 16 8, 16 2, 3 pclkb 2 iclk can 0009 1844h can1 bit configuration register bcr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 1848h can1 receive fifo control register rfcr 8 8 2, 3 pclkb 2 iclk can 0009 1849h can1 receive fifo pointer control register rfpcr 8 8 2, 3 pclkb 2 iclk can 0009 184ah can1 transmit fifo control register tfcr 8 8 2, 3 pclkb 2 iclk can 0009 184bh can1 transmit fifo pointer control register tfpcr 8 8 2, 3 pclkb 2 iclk can 0009 184ch can1 error interrupt enable register eier 8 8 2, 3 pclkb 2 iclk can 0009 184dh can1 error interrupt factor judge register eifr 8 8 2, 3 pclkb 2 iclk can 0009 184eh can1 receive error count register recr 8 8 2, 3 pclkb 2 iclk can 0009 184fh can1 transmit error count register tecr 8 8 2, 3 pclkb 2 iclk can 0009 1850h can1 error code store register ecsr 8 8 2, 3 pclkb 2 iclk can 0009 1851h can1 channel search support register cssr 8 8 2, 3 pclkb 2 iclk can 0009 1852h can1 mailbox search status register mssr 8 8 2, 3 pclkb 2 iclk can 0009 1853h can1 mailbox search mode register msmr 8 8 2, 3 pclkb 2 iclk can 0009 1854h can1 time stamp register tsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 1856h can1 acceptance filter support register afsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 1858h can1 test control register tcr 8 8 2, 3 pclkb 2 iclk can 0009 2200h to 0009 23ffh can2 mailbox registers 0 to 31 mb0 to 31 128 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2400h to 0009 241fh can2 mask registers 0 to 7 mkr0 to 7 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2420h can2 fifo received id compare register 0 fidcr0 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2424h can2 fifo received id compare register 1 fidcr1 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2428h can2 mask invalid register mkivlr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 242ch can2 mailbox interrupt enable register mier 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2820h to 0009 283fh can2 message control registers 0 to 31 mctl0 to 31 8 8 2, 3 pclkb 2 iclk can 0009 2840h can2 control register ctlr 16 8, 16 2, 3 pclkb 2 iclk can 0009 2842h can2 status register str 16 8, 16 2, 3 pclkb 2 iclk can 0009 2844h can2 bit configuration register bcr 32 8, 16, 32 2, 3 pclkb 2 iclk can 0009 2848h can2 receive fifo control register rfcr 8 8 2, 3 pclkb 2 iclk can 0009 2849h can2 receive fifo pointer control register rfpcr 8 8 2, 3 pclkb 2 iclk can 0009 284ah can2 transmit fifo control register tfcr 8 8 2, 3 pclkb 2 iclk can 0009 284bh can2 transmit fifo pointer control register tfpcr 8 8 2, 3 pclkb 2 iclk can 0009 284ch can2 error interrupt enable register eier 8 8 2, 3 pclkb 2 iclk can 0009 284dh can2 error interrupt factor judge register eifr 8 8 2, 3 pclkb 2 iclk can 0009 284eh can2 receive error count register recr 8 8 2, 3 pclkb 2 iclk can 0009 284fh can2 transmit error count register tecr 8 8 2, 3 pclkb 2 iclk can 0009 2850h can2 error code store register ecsr 8 8 2, 3 pclkb 2 iclk can 0009 2851h can2 channel search support register cssr 8 8 2, 3 pclkb 2 iclk can 0009 2852h can2 mailbox search status register mssr 8 8 2, 3 pclkb 2 iclk can 0009 2853h can2 mailbox search mode register msmr 8 8 2, 3 pclkb 2 iclk can table 4.1 list of i/o register s (address order) (40 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 112 of 230 jul 31, 2014 rx64m group 4. i/o registers 0009 2854h can2 time stamp register tsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 2856h can2 acceptance filter support register afsr 16 8, 16 2, 3 pclkb 2 iclk can 0009 2858h can2 test control register tcr 8 8 2, 3 pclkb 2 iclk can 0009 4200h cmtw0 timer start register cmwstr 16 16 2, 3 pclkb 2 iclk cmtw 0009 4204h cmtw0 timer control register cmwcr 16 16 2, 3 pclkb 2 iclk cmtw 0009 4208h cmtw0 timer i/o control register cmwior 16 16 2, 3 pclkb 2 iclk cmtw 0009 4210h cmtw0 timer counter cmwcnt 32 32 2, 3 pclkb 2 iclk cmtw 0009 4214h cmtw0 compare match constant register cmwcor 32 32 2, 3 pclkb 2 iclk cmtw 0009 4218h cmtw0 input capture register 0 cmwicr0 32 32 2, 3 pclkb 2 iclk cmtw 0009 421ch cmtw0 input capture register 1 cmwicr1 32 32 2, 3 pclkb 2 iclk cmtw 0009 4220h cmtw0 output compare register 0 cmwocr0 32 32 2, 3 pclkb 2 iclk cmtw 0009 4224h cmtw0 output compare register 1 cmwocr1 32 32 2, 3 pclkb 2 iclk cmtw 0009 4280h cmtw1 timer start register cmwstr 16 16 2, 3 pclkb 2 iclk cmtw 0009 4284h cmtw1 timer control register cmwcr 16 16 2, 3 pclkb 2 iclk cmtw 0009 4288h cmtw1 timer i/o control register cmwior 16 16 2, 3 pclkb 2 iclk cmtw 0009 4290h cmtw1 timer counter cmwcnt 32 32 2, 3 pclkb 2 iclk cmtw 0009 4294h cmtw1 compare match constant register cmwcor 32 32 2, 3 pclkb 2 iclk cmtw 0009 4298h cmtw1 input capture register 0 cmwicr0 32 32 2, 3 pclkb 2 iclk cmtw 0009 429ch cmtw1 input capture register 1 cmwicr1 32 32 2, 3 pclkb 2 iclk cmtw 0009 42a0h cmtw1 output compare register 0 cmwocr0 32 32 2, 3 pclkb 2 iclk cmtw 0009 42a4h cmtw1 output compare register 1 cmwocr1 32 32 2, 3 pclkb 2 iclk cmtw 0009 8000h to 0009 d6bfh src filter coefficient table srcfctr0 to 5551 32 32 4, 5 pclkb 2, 3 iclk src 0009 dff0h src input data register srcid 32 32 5, 6 pclkb 2, 3 iclk src 0009 dff4h src output data register srcod 32 32 5, 6 pclkb 2, 3 iclk src 0009 dff8h src input data control register srcidctrl 16 16 4, 5 pclkb 2, 3 iclk src 0009 dffah src output data control register srcodctrl 16 16 4, 5 pclkb 2, 3 iclk src 0009 dffch src control register srcctrl 16 16 4, 5 pclkb 2, 3 iclk src 0009 dffeh src status register srcstat 16 16 4, 5 pclkb 2, 3 iclk src 000a 0000h usb0 system configuration control register syscfg 16 16 3, 4 pclkb 2 iclk usbb 000a 0004h usb0 system configuration status register 0 syssts0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0008h usb0 device state control register 0 dvstctr0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0014h usb0 cfifo port register cfifo 16 8, 16 3, 4 pclkb 2 iclk usbb 000a 0018h usb0 d0fifo port register d0fifo 16 8, 16 3, 4 pclkb 2 iclk usbb 000a 001ch usb0 d1fifo port register d1fifo 16 8, 16 3, 4 pclkb 2 iclk usbb 000a 0020h usb0 cfifo port select register cfifosel 16 16 3, 4 pclkb 2 iclk usbb 000a 0022h usb0 cfifo port control register cfifoctr 16 16 3, 4 pclkb 2 iclk usbb 000a 0028h usb0 d0fifo port select register d0fifosel 16 16 3, 4 pclkb 2 iclk usbb 000a 002ah usb0 d0fifo port control register d0fifoctr 16 16 3, 4 pclkb 2 iclk usbb 000a 002ch usb0 d1fifo port select register d1fifosel 16 16 3, 4 pclkb 2 iclk usbb 000a 002eh usb0 d1fifo port control register d1fifoctr 16 16 3, 4 pclkb 2 iclk usbb table 4.1 list of i/o register s (address order) (41 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 113 of 230 jul 31, 2014 rx64m group 4. i/o registers 000a 0030h usb0 interrupt enable register 0 intenb0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0032h usb0 interrupt enable register 1 intenb1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0036h usb0 brdy interrupt enable register brdyenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0038h usb0 nrdy interrupt enable register nrdyenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 003ah usb0 bemp interrupt enable register bempenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 003ch usb0 sof output configuration register sofcfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0040h usb0 interrupt status register 0 intsts0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0042h usb0 interrupt status register 1 intsts1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0046h usb0 brdy interrupt status register brdysts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0048h usb0 nrdy interrupt status register nrdysts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 004ah usb0 bemp interrupt status register bempsts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 004ch usb0 frame number register frmnum 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 004eh usb0 device state change register dvchgr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0050h usb0 usb address register usbaddr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0054h usb0 usb request type register usbreq 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb table 4.1 list of i/o register s (address order) (42 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 114 of 230 jul 31, 2014 rx64m group 4. i/o registers 000a 0056h usb0 usb request value register usbval 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0058h usb0 usb request index register usbindx 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 005ah usb0 usb request length register usbleng 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 005ch usb0 dcp configuration register dcpcfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 005eh usb0 dcp maximum packet size register dcpmaxp 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0060h usb0 dcp control register dcpctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0064h usb0 pipe window select register pipesel 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0068h usb0 pipe configuration register pipecfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 006ch usb0 pipe maximum packet size register pipemaxp 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 006eh usb0 pipe cycle control register pipeperi 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0070h usb0 pipe1 control register pipe1ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0072h usb0 pipe2 control register pipe2ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0074h usb0 pipe3 control register pipe3ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0076h usb0 pipe4 control register pipe4ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0078h usb0 pipe5 control register pipe5ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb table 4.1 list of i/o register s (address order) (43 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 115 of 230 jul 31, 2014 rx64m group 4. i/o registers 000a 007ah usb0 pipe6 control register pipe6ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 007ch usb0 pipe7 control register pipe7ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 007eh usb0 pipe8 control register pipe8ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0080h usb0 pipe9 control register pipe9ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0090h usb0 pipe1 transaction counter enable register pipe1tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0092h usb0 pipe1 transaction counter register pipe1trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0094h usb0 pipe2 transaction counter enable register pipe2tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0096h usb0 pipe2 transaction counter register pipe2trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0098h usb0 pipe3 transaction counter enable register pipe3tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 009ah usb0 pipe3 transaction counter register pipe3trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 009ch usb0 pipe4 transaction counter enable register pipe4tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 009eh usb0 pipe4 transaction counter register pipe4trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00a0h usb0 pipe5 transaction counter enable register pipe5tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00a2h usb0 pipe5 transaction counter register pipe5trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00d0h usb0 device address 0 configuration register devadd0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb table 4.1 list of i/o register s (address order) (44 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 116 of 230 jul 31, 2014 rx64m group 4. i/o registers 000a 00d2h usb0 device address 1 configuration register devadd1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00d4h usb0 device address 2 configuration register devadd2 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00d6h usb0 device address 3 configuration register devadd3 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00d8h usb0 device address 4 configuration register devadd4 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00dah usb0 device address 5 configuration register devadd5 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 00f0h usb0 phy cross point adjustment register physlew 32 32 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0400h usb deep standby usb transceiver control/pin monitoring register dpusr0r 32 32 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0404h usb deep standby usb suspend/resume interrupt register dpusr1r 32 32 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/ pclkb)* 5 usbb 000a 0500h pdc pdc control register 0 pccr0 32 32 2, 3 pclkb 2 iclk pdc 000a 0504h pdc pdc control register 1 pccr1 32 32 2, 3 pclkb 2 iclk pdc 000a 0508h pdc pdc status register pcsr 32 32 2, 3 pclkb 2 iclk pdc 000a 050ch pdc pdc pin monitor register pcmonr 32 32 2, 3 pclkb 2 iclk pdc 000a 0510h pdc pdc receive data register pcdr 32 32 2, 3 pclkb 2 iclk pdc 000a 0514h pdc vertical capture register vcr 32 32 2, 3 pclkb 2 iclk pdc 000a 0518h pdc horizontal capture register hcr 32 32 2, 3 pclkb 2 iclk pdc 000c 0000h edmac 0 edmac mode register edmr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0008h edmac 0 edmac transmit request register edtrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0010h edmac 0 edmac receive request register edrrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0018h edmac 0 transmit descriptor list start address register tdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0020h edmac 0 receive descriptor list start address register rdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0028h edmac 0 etherc/edmac status register eesr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0030h edmac 0 etherc/edmac status interrupt enable register eesipr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0038h edmac 0 etherc/edmac transmit/receive status copy enable register trscer 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0040h edmac 0 missed-frame counter register rmfcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0048h edmac 0 transmit fifo threshold register tftr 32 32 4, 5 pclka 2, 3 iclk edmac a table 4.1 list of i/o register s (address order) (45 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 117 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 0050h edmac 0 fifo depth register fdr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0058h edmac 0 receive method control register rmcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0064h edmac 0 transmit fifo underflow counter tfucr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0068h edmac 0 receive fifo overflow counter rfocr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 006ch edmac 0 independent output signal setting register iosr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0070h edmac 0 flow control start fifo threshold setting register fcftr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0078h edmac 0 receive data padding insert register rpadir 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 007ch edmac 0 transmit interrupt setting register trimd 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 00c8h edmac 0 receive buffer write address register rbwar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 00cch edmac 0 receive descriptor fetch address register rdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 00d4h edmac 0 transmit buffer read address register tbrar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 00d8h edmac 0 transmit descriptor fetch address register tdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0100h ether c0 etherc mode register ecmr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0108h ether c0 receive frame length register rflr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0110h ether c0 etherc status register ecsr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0118h ether c0 etherc interrupt enable register ecsipr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0120h ether c0 phy interface register pir 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0128h ether c0 phy status register psr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0140h ether c0 random number generation counter upper limit setting register rdmlr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0150h ether c0 ipg register ipgr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0154h ether c0 automatic pause frame register apr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0158h ether c0 manual pause frame register mpr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0160h ether c0 received pause frame counter rfcf 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0164h ether c0 pause frame retransmit count setting register tpauser 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0168h ether c0 pause frame retransmit counter tpausecr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 016ch ether c0 broadcast frame receive count setting register bcfrr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01c0h ether c0 mac address upper bit register mahr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01c8h ether c0 mac address lower bit register malr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01d0h ether c0 transmit retry over counter register trocr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01d4h ether c0 late collision detect counter register cdcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01d8h ether c0 lost carrier counter register lccr 32 32 13, 14 pclka 2 to 7 iclk ether c table 4.1 list of i/o register s (address order) (46 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 118 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 01dch ether c0 carrier not detect counter register cndcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01e4h ether c0 crc error frame receive counter register cefcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01e8h ether c0 frame receive error counter register frecr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01ech ether c0 too-short frame receive counter register tsfrcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01f0h ether c0 too-long frame receive counter register tlfrcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01f4h ether c0 received alignment error frame counter register rfcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 01f8h ether c0 multicast address frame receive counter register mafcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0200h edmac 1 edmac mode register edmr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0208h edmac 1 edmac transmit request register edtrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0210h edmac 1 edmac receive request register edrrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0218h edmac 1 transmit descriptor list start address register tdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0220h edmac 1 receive descriptor list start address register rdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0228h edmac 1 etherc/edmac status register eesr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0230h edmac 1 etherc/edmac status interrupt enable register eesipr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0238h edmac 1 etherc/edmac transmit/receive status copy enable register trscer 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0240h edmac 1 missed-frame counter register rmfcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0248h edmac 1 transmit fifo threshold register tftr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0250h edmac 1 fifo depth register fdr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0258h edmac 1 receive method control register rmcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0264h edmac 1 transmit fifo underflow counter tfucr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0268h edmac 1 receive fifo overflow counter rfocr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 026ch edmac 1 independent output signal setting register iosr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0270h edmac 1 flow control start fifo threshold setting register fcftr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0278h edmac 1 receive data padding insert register rpadir 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 027ch edmac 1 transmit interrupt setting register trimd 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 02c8h edmac 1 receive buffer write address register rbwar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 02cch edmac 1 receive descriptor fetch address register rdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 02d4h edmac 1 transmit buffer read address register tbrar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 02d8h edmac 1 transmit descriptor fetch address register tdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0300h ether c1 etherc mode register ecmr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0308h ether c1 receive frame length register rflr 32 32 13, 14 pclka 2 to 7 iclk ether c table 4.1 list of i/o register s (address order) (47 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 119 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 0310h ether c1 etherc status register ecsr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0318h ether c1 etherc interrupt enable register ecsipr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0320h ether c1 phy interface register pir 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0328h ether c1 phy status register psr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0340h ether c1 random number generation counter upper limit setting register rdmlr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0350h ether c1 ipg register ipgr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0354h ether c1 automatic pause frame register apr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0358h ether c1 manual pause frame register mpr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0360h ether c1 received pause frame counter rfcf 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0364h ether c1 pause frame retransmit count setting register tpauser 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0368h ether c1 pause frame retransmit counter register tpausecr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 036ch ether c1 broadcast frame receive count setting register bcfrr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03c0h ether c1 mac address upper bit register mahr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03c8h ether c1 mac address lower bit register malr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03d0h ether c1 transmit retry over counter register trocr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03d4h ether c1 late collision detect counter register cdcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03d8h ether c1 lost carrier counter register lccr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03dch ether c1 carrier not detect counter register cndcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03e4h ether c1 crc error frame receive counter register cefcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03e8h ether c1 frame receive error counter register frecr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03ech ether c1 too-short frame receive counter register tsfrcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03f0h ether c1 too-long frame receive counter register tlfrcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03f4h ether c1 received alignment error frame counter register rfcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 03f8h ether c1 multicast address frame receive counter register mafcr 32 32 13, 14 pclka 2 to 7 iclk ether c 000c 0400h ptped mac edmac mode register edmr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0408h ptped mac edmac transmit request register edtrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0410h ptped mac edmac receive request register edrrr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0418h ptped mac transmit descriptor list start address register tdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0420h ptped mac receive descriptor list start address register rdlar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0428h ptped mac ptp/edmac status register eesr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0430h ptped mac ptp/edmac status interrupt enable register eesipr 32 32 4, 5 pclka 2, 3 iclk edmac a table 4.1 list of i/o register s (address order) (48 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 120 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 0438h ptped mac ptp/edmac transmit/receive status copy enable register trscer 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0440h ptped mac missed-frame counter register rmfcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0448h ptped mac transmit fifo threshold register tftr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0450h ptped mac fifo depth register fdr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0458h ptped mac receive method control register rmcr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0464h ptped mac transmit fifo underflow counter tfucr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0468h ptped mac receive fifo overflow counter rfocr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 046ch ptped mac independent output signal setting register iosr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0470h ptped mac flow control start fifo threshold setting register fcftr 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0478h ptped mac receive data padding insert register rpadir 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 047ch ptped mac transmit interrupt setting register trimd 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 04c8h ptped mac receive buffer write address register rbwar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 04cch ptped mac receive descriptor fetch address register rdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 04d4h ptped mac transmit buffer read address register tbrar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 04d8h ptped mac transmit descriptor fetch address register tdfar 32 32 4, 5 pclka 2, 3 iclk edmac a 000c 0500h eptpc ptp reset register ptrstr 32 32 3, 4 pclka 2, 3 iclk eptpc 000c 0504h eptpc stca clock select register stcselr 32 32 3, 4 pclka 2, 3 iclk eptpc 000c 1200h mtu3 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1201h mtu4 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1202h mtu3 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1203h mtu4 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1204h mtu3 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1205h mtu3 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1206h mtu4 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1207h mtu4 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1208h mtu3 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1209h mtu4 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 120ah mtu timer output master enable register a toera 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 120dh mtu timer gate control register a tgcra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 120eh mtu timer output control register 1a tocr1a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 120fh mtu timer output control register 2a tocr2a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1210h mtu3 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1212h mtu4 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1214h mtu timer cycle data register a tcdra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1216h mtu timer dead time data register a tddra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1218h mtu3 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 121ah mtu3 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 121ch mtu4 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 121eh mtu4 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1220h mtu timer subcounter a tcntsa 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1222h mtu timer cycle buffer register a tcbra 16 16 5, 6 pclka 2, 3 iclk mtu3a table 4.1 list of i/o register s (address order) (49 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 121 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 1224h mtu3 timer general register c tgrc 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1226h mtu3 timer general register d tgrd 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1228h mtu4 timer general register c tgrc 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 122ah mtu4 timer general register d tgrd 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 122ch mtu3 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 122dh mtu4 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1230h mtu timer interrupt skipping set register 1a titcr1a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1231h mtu timer interrupt skipping counter 1a titcnt1a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1232h mtu timer buffer transfer set register a tbtera 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1234h mtu timer dead time enable register a tdera 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1236h mtu timer output level buffer register a tolbra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1238h mtu3 timer buffer operation transfer mode register tbtm 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1239h mtu4 timer buffer operation transfer mode register tbtm 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 123ah mtu timer interrupt skipping mode register a titmra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 123bh mtu timer interrupt skipping set register 2a titcr2a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 123ch mtu timer interrupt skipping counter 2a titcnt2a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1240h mtu4 timer a/d converter start request control register tadcr 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1244h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1246h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1248h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 124ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 124ch mtu3 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 124dh mtu4 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1260h mtu timer waveform control register a twcra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1270h mtu timer mode register 2a tmdr2a 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1272h mtu3 timer general register e tgre 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1274h mtu4 timer general register e tgre 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1276h mtu4 timer general register f tgrf 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1280h mtu timer start register a tstra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1281h mtu timer synchronous register a tsyra 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1282h mtu timer counter synchronous start register tcsystr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1284h mtu timer read/write enable register a trwera 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1290h mtu0 noise filter control register 0 nfcr0 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1291h mtu1 noise filter control register 1 nfcr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1292h mtu2 noise filter control register 2 nfcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1293h mtu3 noise filter control register 3 nfcr3 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1294h mtu4 noise filter control register 4 nfcr4 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1298h mtu8 noise filter control register 8 nfcr8 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1299h mtu0 noise filter control register c nfcrc 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1300h mtu0 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1301h mtu0 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1302h mtu0 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1303h mtu0 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1304h mtu0 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1306h mtu0 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1308h mtu0 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 130ah mtu0 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a table 4.1 list of i/o register s (address order) (50 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 122 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 130ch mtu0 timer general register c tgrc 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 130eh mtu0 timer general register d tgrd 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1320h mtu0 timer general register e tgre 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1322h mtu0 timer general register f tgrf 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1324h mtu0 timer interrupt enable register 2 tier2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1325h mtu0 timer status register 2 tsr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1326h mtu0 timer buffer operation transfer mode register tbtm 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1328h mtu0 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1380h mtu1 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1381h mtu1 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1382h mtu1 timer i/o control register tior 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1384h mtu1 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1385h mtu1 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1386h mtu1 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1388h mtu1 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 138ah mtu1 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1390h mtu1 timer input capture control register ticcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1391h mtu1 timer mode register 3 tmdr3 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1394h mtu1 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 13a0h mtu1 timer longword counter tcntlw 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 13a4h mtu1 timer longword general register tgralw 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 13a8h mtu1 timer longword general register tgrblw 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 1400h mtu2 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1401h mtu2 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1402h mtu2 timer i/o control register tior 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1404h mtu2 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1405h mtu2 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1406h mtu2 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1408h mtu2 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 140ah mtu2 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 140ch mtu2 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1600h mtu8 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1601h mtu8 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1602h mtu8 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1603h mtu8 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1604h mtu8 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1606h mtu8 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1608h mtu8 timer counter tcnt 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 160ch mtu8 timer general register a tgra 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 1610h mtu8 timer general register b tgrb 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 1614h mtu8 timer general register c tgrc 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 1618h mtu8 timer general register d tgrd 32 32 5, 6 pclka 2, 3 iclk mtu3a 000c 1a00h mtu6 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a01h mtu7 timer control register tcr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a02h mtu6 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a03h mtu7 timer mode register 1 tmdr1 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a04h mtu6 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a05h mtu6 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a06h mtu7 timer i/o control register h tiorh 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a07h mtu7 timer i/o control register l tiorl 8 8 5, 6 pclka 2, 3 iclk mtu3a table 4.1 list of i/o register s (address order) (51 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 123 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 1a08h mtu6 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a09h mtu7 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a0ah mtu timer output master enable register b toerb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a0eh mtu timer output control register 1b tocr1b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a0fh mtu timer output control register 2b tocr2b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a10h mtu6 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a12h mtu7 timer counter tcnt 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a14h mtu timer cycle data register b tcdrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a16h mtu timer dead time data register b tddrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a18h mtu6 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a1ah mtu6 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a1ch mtu7 timer general register a tgra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a1eh mtu7 timer general register b tgrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a20h mtu timer subcounter b tcntsb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a22h mtu timer cycle buffer register b tcbrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a24h mtu6 timer general register c tgrc 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a26h mtu6 timer general register d tgrd 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a28h mtu7 timer general register c tgrc 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a2ah mtu7 timer general register d tgrd 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a2ch mtu6 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a2dh mtu7 timer status register tsr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a30h mtu timer interrupt skipping set register 1b titcr1b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a31h mtu timer interrupt skipping counter 1b titcnt1b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a32h mtu timer buffer transfer set register b tbterb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a34h mtu timer dead time enable register b tderb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a36h mtu timer output level buffer register b tolbrb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a38h mtu6 timer buffer operation transfer mode register tbtm 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a39h mtu7 timer buffer operation transfer mode register tbtm 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a3ah mtu timer interrupt skipping mode register b titmrb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a3bh mtu timer interrupt skipping set register 2b titcr2b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a3ch mtu timer interrupt skipping counter 2b titcnt2b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a40h mtu7 timer a/d converter start request control register tadcr 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a44h mtu7 timer a/d converter start request cycle set register a tadcora 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a46h mtu7 timer a/d converter start request cycle set register b tadcorb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a48h mtu7 timer a/d converter start request cycle set buffer register a tadcobra 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a4ah mtu7 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a4ch mtu6 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a4dh mtu7 timer control register 2 tcr2 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a50h mtu6 timer synchronous clear register tsycr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a60h mtu timer waveform control register b twcrb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a70h mtu timer mode register 2b tmdr2b 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a72h mtu6 timer general register e tgre 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a74h mtu7 timer general register e tgre 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a76h mtu7 timer general register f tgrf 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1a80h mtu timer start register b tstrb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a81h mtu timer synchronous register b tsyrb 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a84h mtu timer read/write enable register b trwerb 8 8 5, 6 pclka 2, 3 iclk mtu3a table 4.1 list of i/o register s (address order) (52 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 124 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 1a93h mtu6 noise filter control register 6 nfcr6 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a94h mtu7 noise filter control register 7 nfcr7 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1a95h mtu5 noise filter control register 5 nfcr5 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c80h mtu5 timer counter u tcntu 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1c82h mtu5 timer general register u tgru 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1c84h mtu5 timer control register u tcru 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c85h mtu5 timer control register 2 tcr2u 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c86h mtu5 timer i/o control register u tioru 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c90h mtu5 timer counter v tcntv 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1c92h mtu5 timer general register v tgrv 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1c94h mtu5 timer control register v tcrv 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c95h mtu5 timer control register 2 tcr2v 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1c96h mtu5 timer i/o control register v tiorv 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1ca0h mtu5 timer counter w tcntw 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1ca2h mtu5 timer general register w tgrw 16 16 5, 6 pclka 2, 3 iclk mtu3a 000c 1ca4h mtu5 timer control register w tcrw 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1ca5h mtu5 timer control register 2 tcr2w 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1ca6h mtu5 timer i/o control register w tiorw 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1cb2h mtu5 timer interrupt enable register tier 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1cb4h mtu5 timer start register tstr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 1cb6h mtu5 timer compare match clear register tcntcmpclr 8 8 5, 6 pclka 2, 3 iclk mtu3a 000c 2000h gpt general pwm timer software start register gtstr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2002h gpt noise filter control register nfcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2004h gpt general pwm timer hardware source start/stop control register gthscr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2006h gpt general pwm timer hardware source clear control register gthccr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2008h gpt general pwm timer hardware start source select register gthssr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 200ah gpt general pwm timer hardware stop/clear source select register gthpsr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 200ch gpt general pwm timer write-protection register gtwp 16 16 4, 5 pclka 2, 3 iclk gpta 000c 200eh gpt general pwm timer sync register gtsync 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2010h gpt general pwm timer external trigger input interrupt register gtetint 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2014h gpt general pwm timer buffer operation disable register gtbdr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2018h gpt general pwm timer start write-protection register gtswp 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2100h gpt0 general pwm timer i/o control register gtior 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2102h gpt0 general pwm timer interrupt output setting register gtintad 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2104h gpt0 general pwm timer control register gtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2106h gpt0 general pwm timer buffer enable register gtber 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2108h gpt0 general pwm timer count direction register gtudc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 210ah gpt0 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 210ch gpt0 general pwm timer status register gtst 16 16 4, 5 pclka 2, 3 iclk gpta 000c 210eh gpt0 general pwm timer counter gtcnt 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2110h gpt0 general pwm timer compare capture register a gtccra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2112h gpt0 general pwm timer compare capture register b gtccrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2114h gpt0 general pwm timer compare capture register c gtccrc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2116h gpt0 general pwm timer compare capture register d gtccrd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2118h gpt0 general pwm timer compare capture register e gtccre 16 16 4, 5 pclka 2, 3 iclk gpta table 4.1 list of i/o register s (address order) (53 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 125 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 211ah gpt0 general pwm timer compare capture register f gtccrf 16 16 4, 5 pclka 2, 3 iclk gpta 000c 211ch gpt0 general pwm timer cycle setting register gtpr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 211eh gpt0 general pwm timer cycle setting buffer register gtpbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2120h gpt0 general pwm timer cycle setting double-buffer register gtpdbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2124h gpt0 a/d converter start request timing register a gtadtra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2126h gpt0 a/d converter start request timing buffer register a gtadtbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2128h gpt0 a/d converter start request timing double-buffer register a gtadtdbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 212ch gpt0 a/d converter start request timing register b gtadtrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 212eh gpt0 a/d converter start request timing buffer register b gtadtbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2130h gpt0 a/d converter start request timing double-buffer register b gtadtdbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2134h gpt0 general pwm timer output negate control register gtoncr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2136h gpt0 general pwm timer dead time control register gtdtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2138h gpt0 general pwm timer dead time value register u gtdvu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 213ah gpt0 general pwm timer dead time value register d gtdvd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 213ch gpt0 general pwm timer dead time buffer register u gtdbu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 213eh gpt0 general pwm timer dead time buffer register d gtdbd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2140h gpt0 general pwm timer output protection function status register gtsos 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2142h gpt0 general pwm timer output protection function temporary release register gtsotr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2180h gpt1 general pwm timer i/o control register gtior 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2182h gpt1 general pwm timer interrupt output setting register gtintad 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2184h gpt1 general pwm timer control register gtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2186h gpt1 general pwm timer buffer enable register gtber 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2188h gpt1 general pwm timer count direction register gtudc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 218ah gpt1 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 218ch gpt1 general pwm timer status register gtst 16 16 4, 5 pclka 2, 3 iclk gpta 000c 218eh gpt1 general pwm timer counter gtcnt 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2190h gpt1 general pwm timer compare capture register a gtccra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2192h gpt1 general pwm timer compare capture register b gtccrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2194h gpt1 general pwm timer compare capture register c gtccrc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2196h gpt1 general pwm timer compare capture register d gtccrd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2198h gpt1 general pwm timer compare capture register e gtccre 16 16 4, 5 pclka 2, 3 iclk gpta 000c 219ah gpt1 general pwm timer compare capture register f gtccrf 16 16 4, 5 pclka 2, 3 iclk gpta 000c 219ch gpt1 general pwm timer cycle setting register gtpr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 219eh gpt1 general pwm timer cycle setting buffer register gtpbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21a0h gpt1 general pwm timer cycle setting double-buffer register gtpdbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21a4h gpt1 a/d converter start request timing register a gtadtra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21a6h gpt1 a/d converter start request timing buffer register a gtadtbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21a8h gpt1 a/d converter start request timing double-buffer register a gtadtdbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21ach gpt1 a/d converter start request timing register b gtadtrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21aeh gpt1 a/d converter start request timing buffer register b gtadtbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21b0h gpt1 a/d converter start request timing double-buffer register b gtadtdbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21b4h gpt1 general pwm timer output negate control register gtoncr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21b6h gpt1 general pwm timer dead time control register gtdtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21b8h gpt1 general pwm timer dead time value register u gtdvu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21bah gpt1 general pwm timer dead time value register d gtdvd 16 16 4, 5 pclka 2, 3 iclk gpta table 4.1 list of i/o register s (address order) (54 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 126 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 21bch gpt1 general pwm timer dead time buffer register u gtdbu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21beh gpt1 general pwm timer dead time buffer register d gtdbd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21c0h gpt1 general pwm timer output protection function status register gtsos 16 16 4, 5 pclka 2, 3 iclk gpta 000c 21c2h gpt1 general pwm timer output protection function temporary release register gtsotr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2200h gpt2 general pwm timer i/o control register gtior 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2202h gpt2 general pwm timer interrupt output setting register gtintad 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2204h gpt2 general pwm timer control register gtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2206h gpt2 general pwm timer buffer enable register gtber 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2208h gpt2 general pwm timer count direction register gtudc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 220ah gpt2 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 220ch gpt2 general pwm timer status register gtst 16 16 4, 5 pclka 2, 3 iclk gpta 000c 220eh gpt2 general pwm timer counter gtcnt 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2210h gpt2 general pwm timer compare capture register a gtccra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2212h gpt2 general pwm timer compare capture register b gtccrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2214h gpt2 general pwm timer compare capture register c gtccrc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2216h gpt2 general pwm timer compare capture register d gtccrd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2218h gpt2 general pwm timer compare capture register e gtccre 16 16 4, 5 pclka 2, 3 iclk gpta 000c 221ah gpt2 general pwm timer compare capture register f gtccrf 16 16 4, 5 pclka 2, 3 iclk gpta 000c 221ch gpt2 general pwm timer cycle setting register gtpr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 221eh gpt2 general pwm timer cycle setting buffer register gtpbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2220h gpt2 general pwm timer cycle setting double-buffer register gtpdbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2224h gpt2 a/d converter start request timing register a gtadtra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2226h gpt2 a/d converter start request timing buffer register a gtadtbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2228h gpt2 a/d converter start request timing double-buffer register a gtadtdbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 222ch gpt2 a/d converter start request timing register b gtadtrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 222eh gpt2 a/d converter start request timing buffer register b gtadtbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2230h gpt2 a/d converter start request timing double-buffer register b gtadtdbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2234h gpt2 general pwm timer output negate control register gtoncr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2236h gpt2 general pwm timer dead time control register gtdtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2238h gpt2 general pwm timer dead time value register u gtdvu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 223ah gpt2 general pwm timer dead time value register d gtdvd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 223ch gpt2 general pwm timer dead time buffer register u gtdbu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 223eh gpt2 general pwm timer dead time buffer register d gtdbd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2240h gpt2 general pwm timer output protection function status register gtsos 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2242h gpt2 general pwm timer output protection function temporary release register gtsotr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2280h gpt3 general pwm timer i/o control register gtior 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2282h gpt3 general pwm timer interrupt output setting register gtintad 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2284h gpt3 general pwm timer control register gtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2286h gpt3 general pwm timer buffer enable register gtber 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2288h gpt3 general pwm timer count direction register gtudc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 228ah gpt3 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 228ch gpt3 general pwm timer status register gtst 16 16 4, 5 pclka 2, 3 iclk gpta 000c 228eh gpt3 general pwm timer counter gtcnt 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2290h gpt3 general pwm timer compare capture register a gtccra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2292h gpt3 general pwm timer compare capture register b gtccrb 16 16 4, 5 pclka 2, 3 iclk gpta table 4.1 list of i/o register s (address order) (55 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 127 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 2294h gpt3 general pwm timer compare capture register c gtccrc 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2296h gpt3 general pwm timer compare capture register d gtccrd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 2298h gpt3 general pwm timer compare capture register e gtccre 16 16 4, 5 pclka 2, 3 iclk gpta 000c 229ah gpt3 general pwm timer compare capture register f gtccrf 16 16 4, 5 pclka 2, 3 iclk gpta 000c 229ch gpt3 general pwm timer cycle setting register gtpr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 229eh gpt3 general pwm timer cycle setting buffer register gtpbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22a0h gpt3 general pwm timer cycle setting double-buffer register gtpdbr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22a4h gpt3 a/d converter start request timing register a gtadtra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22a6h gpt3 a/d converter start request timing buffer register a gtadtbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22a8h gpt3 a/d converter start request timing double-buffer register a gtadtdbra 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22ach gpt3 a/d converter start request timing register b gtadtrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22aeh gpt3 a/d converter start request timing buffer register b gtadtbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22b0h gpt3 a/d converter start request timing double-buffer register b gtadtdbrb 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22b4h gpt3 general pwm timer output negate control register gtoncr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22b6h gpt3 general pwm timer dead time control register gtdtcr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22b8h gpt3 general pwm timer dead time value register u gtdvu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22bah gpt3 general pwm timer dead time value register d gtdvd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22bch gpt3 general pwm timer dead time buffer register u gtdbu 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22beh gpt3 general pwm timer dead time buffer register d gtdbd 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22c0h gpt3 general pwm timer output protection function status register gtsos 16 16 4, 5 pclka 2, 3 iclk gpta 000c 22c2h gpt3 general pwm timer output protection function temporary release register gtsotr 16 16 4, 5 pclka 2, 3 iclk gpta 000c 4000h eptpc mint interrupt source status register miesr 32 32 5, 6 pclka 2, 3 iclk eptpc 000c 4004h eptpc mint interrupt request permission register mieipr 32 32 5, 6 pclka 2, 3 iclk eptpc 000c 4010h eptpc elc output/ipls interrupt request permission register elippr 32 32 5, 6 pclka 2, 3 iclk eptpc 000c 4014h eptpc elc output/ipls interrupt permission automatic clearing register elipacr 32 32 5, 6 pclka 2, 3 iclk eptpc 000c 4040h eptpc stca status register stsr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4044h eptpc stca status notification permission register stipr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4050h eptpc stca clock frequency setting register stcfr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4054h eptpc stca operating mode register stmr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4058h eptpc sync message reception timeout register syntor 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4060h eptpc ipls interrupt request timer select register iptselr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4064h eptpc mint interrupt request timer select register mitselr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4068h eptpc elc output timer select register eltselr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 406ch eptpc time synchronization channel select register stchselr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4080h eptpc slave time synchronization start register synstartr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4084h eptpc local time counter initial value load directive register lcivldr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4090h eptpc synchronization loss detection threshold register syntdaru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4094h eptpc synchronization loss detection threshold register syntdarl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4098h eptpc synchronization detection threshold register syntdbru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 409ch eptpc synchronization detection threshold register syntdbrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 40b0h eptpc local time counter initial value register lcivru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 40b4h eptpc local time counter initial value register lcivrm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 40b8h eptpc local time counter initial value register lcivrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4124h eptpc worst 10 acquisition directive register getw10r 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4128h eptpc positive gradient limit register plimitru 32 32 8 to 43 pclka 2 to 22 iclk eptpc table 4.1 list of i/o register s (address order) (56 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 128 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 412ch eptpc positive gradient limit register plimitrm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4130h eptpc positive gradient limit register plimitrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4134h eptpc negative gradient limit register mlimitru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4138h eptpc negative gradient limit register mlimitrm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 413ch eptpc negative gradient limit register mlimitrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4140h eptpc statistical information retention control register getinfor 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4170h eptpc local time counter lccvru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4174h eptpc local time counter lccvrm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4178h eptpc local time counter lccvrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4210h eptpc positive gradient worst 10 value register pw10vru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4214h eptpc positive gradient worst 10 value register pw10vrm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4218h eptpc positive gradient worst 10 value register pw10vrl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 42d0h eptpc negative gradient worst 10 value register mw10ru 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 42d4h eptpc negative gradient worst 10 value register mw10rm 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 42d8h eptpc negative gradient worst 10 value register mw10rl 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4300h eptpc timer start time setting register tmsttru0 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4304h eptpc timer start time setting register tmsttrl0 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4308h eptpc timer cycle setting register 0 tmcycr0 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 430ch eptpc timer pulse width setting register 0 tmplsr0 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4310h eptpc timer start time setting register tmsttru1 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4314h eptpc timer start time setting register tmsttrl1 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4318h eptpc timer cycle setting register 1 tmcycr1 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 431ch eptpc timer pulse width setting register 1 tmplsr1 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4320h eptpc timer start time setting register tmsttru2 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4324h eptpc timer start time setting register tmsttrl2 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4328h eptpc timer cycle setting register 2 tmcycr2 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 432ch eptpc timer pulse width setting register 2 tmplsr2 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4330h eptpc timer start time setting register tmsttru3 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4334h eptpc timer start time setting register tmsttrl3 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4338h eptpc timer cycle setting register 3 tmcycr3 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 433ch eptpc timer pulse width setting register 3 tmplsr3 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4340h eptpc timer start time setting register tmsttru4 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4344h eptpc timer start time setting register tmsttrl4 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4348h eptpc timer cycle setting register 4 tmcycr4 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 434ch eptpc timer pulse width setting register 4 tmplsr4 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4350h eptpc timer start time setting register tmsttru5 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4354h eptpc timer start time setting register tmsttrl5 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4358h eptpc timer cycle setting register 5 tmcycr5 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 435ch eptpc timer pulse width setting register 5 tmplsr5 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 437ch eptpc timer start register tmstartr 32 32 8 to 43 pclka 2 to 22 iclk eptpc 000c 4400h eptpc prc-tc status register prsr 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4404h eptpc prc-tc status notification permission register pripr 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4410h eptpc channel 0 local mac address register prmacru0 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4414h eptpc channel 0 local mac address register prmacrl0 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4418h eptpc channel 1 local mac address register prmacru1 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 441ch eptpc channel 1 local mac address register prmacrl1 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4420h eptpc packet transmission control register trndisr 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4430h eptpc relay mode register trnmr 32 32 9, 10 pclka 2 to 5 iclk eptpc 000c 4434h eptpc cut-through transfer start threshold register trncttdr 32 32 9, 10 pclka 2 to 5 iclk eptpc table 4.1 list of i/o register s (address order) (57 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 129 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 4800h eptpc 0 synfp status register sysr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4804h eptpc 0 synfp status notification permission register syipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4810h eptpc 0 synfp mac address register symacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4814h eptpc 0 synfp mac address register symacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 481ch eptpc 0 synfp local ip address register syipaddrr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4840h eptpc 0 synfp specification version setting register syspvrr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4844h eptpc 0 synfp domain number setting register sydomr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4850h eptpc 0 announce message flag field setting register anfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4854h eptpc 0 sync message flag field setting register synfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4858h eptpc 0 delay_req message flag field setting register dyrqfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 485ch eptpc 0 delay_resp message flag field setting register dyrpfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4860h eptpc 0 synfp local clock id registers sycidru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4864h eptpc 0 synfp local clock id registers sycidrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4868h eptpc 0 synfp local port number register sypnumr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4880h eptpc 0 synfp register value load directive register syrvldr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4890h eptpc 0 synfp reception filter register 1 syrfl1r 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4894h eptpc 0 synfp reception filter register 2 syrfl2r 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4898h eptpc 0 synfp transmission enable register sytrenr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48a0h eptpc 0 master clock id register mtcidu 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48a4h eptpc 0 master clock id register mtcidl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48a8h eptpc 0 master clock port number register mtpid 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48c0h eptpc 0 synfp transmission interval setting register sytlir 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48c4h eptpc 0 synfp received logmessageinterval value indication register syrlir 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48c8h eptpc 0 offsetfrommaster value register ofmru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48cch eptpc 0 offsetfrommaster value register ofmrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48d0h eptpc 0 meanpathdelay value register mpdru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48d4h eptpc 0 meanpathdelay value register mpdrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48e0h eptpc 0 grandmasterpriority field setting register gmpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48e4h eptpc 0 grandmasterclockquality field setting register gmcqr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48e8h eptpc 0 grandmasteridentity field setting registers gmidru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48ech eptpc 0 grandmasteridentity field setting registers gmidrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc table 4.1 list of i/o register s (address order) (58 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 130 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 48f0h eptpc 0 currentutcoffset/timesource field setting register cuotsr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 48f4h eptpc 0 stepsremoved field setting register srr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4900h eptpc 0 ptp-primary message destination mac address setting registers ppmacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4904h eptpc 0 ptp-primary message destination mac address setting registers ppmacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4908h eptpc 0 ptp-pdelay message mac address setting registers pdmacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 490ch eptpc 0 ptp-pdelay message mac address setting registers pdmacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4910h eptpc 0 ptp message ethertype setting register petyper 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4920h eptpc 0 ptp-primary message destination ip address setting register ppipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4924h eptpc 0 ptp-pdelay message destination ip address setting register pdipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4928h eptpc 0 ptp event message tos setting register petosr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 492ch eptpc 0 ptp general message tos setting register pgtosr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4930h eptpc 0 ptp-primary message ttl setting register ppttlr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4934h eptpc 0 ptp-pdelay message ttl setting register pdttlr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4938h eptpc 0 ptp event message udp destination port number setting register peudpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 493ch eptpc 0 ptp general message udp destination port number setting register pgudpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4940h eptpc 0 frame reception filter setting register ffltr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4960h eptpc 0 frame reception filter mac address 0 setting registers fmac0ru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4964h eptpc 0 frame reception filter mac address 0 setting registers fmac0rl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4968h eptpc 0 frame reception filter mac address 1 setting registers fmac1ru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 496ch eptpc 0 frame reception filter mac address 1 setting registers fmac1rl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49c0h eptpc 0 asymmetric delay setting register dasymru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49c4h eptpc 0 asymmetric delay setting register dasymrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49c8h eptpc 0 timestamp latency setting register tslatr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49cch eptpc 0 synfp operation setting register syconfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49d0h eptpc 0 synfp frame format setting register syformr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 49d4h eptpc 0 response message reception timeout register rstoutr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c00h eptpc 1 synfp status register sysr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c04h eptpc 1 synfp status notification permission register syipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c10h eptpc 1 synfp mac address registers symacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c14h eptpc 1 synfp mac address registers symacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c1ch eptpc 1 synfp local ip address register syipaddrr 32 32 9 to 211 pclka 2 to 106 iclk eptpc table 4.1 list of i/o register s (address order) (59 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 131 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 4c40h eptpc 1 synfp specification version setting register syspvrr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c44h eptpc 1 synfp domain number setting register sydomr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c50h eptpc 1 announce message flag field setting register anfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c54h eptpc 1 sync message flag field setting register synfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c58h eptpc 1 delay_req message flag field setting register dyrqfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c5ch eptpc 1 delay_resp message flag field setting register dyrpfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c60h eptpc 1 synfp local clock id registers sycidru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c64h eptpc 1 synfp local clock id registers sycidrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c68h eptpc 1 synfp local port number register sypnumr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c80h eptpc 1 synfp register value load directive register syrvldr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c90h eptpc 1 synfp reception filter register 1 syrfl1r 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c94h eptpc 1 synfp reception filter register 2 syrfl2r 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4c98h eptpc 1 synfp transmission enable register sytrenr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ca0h eptpc 1 master clock id register mtcidu 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ca4h eptpc 1 master clock id register mtcidl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ca8h eptpc 1 master clock port number register mtpid 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cc0h eptpc 1 synfp transmission interval setting register sytlir 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cc4h eptpc 1 synfp received logmessageinterval value indication register syrlir 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cc8h eptpc 1 offsetfrommaster value register ofmru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ccch eptpc 1 offsetfrommaster value register ofmrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cd0h eptpc 1 meanpathdelay value register mpdru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cd4h eptpc 1 meanpathdelay value register mpdrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ce0h eptpc 1 grandmasterpriority field setting register gmpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ce4h eptpc 1 grandmasterclockquality field setting register gmcqr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4ce8h eptpc 1 grandmasteridentity field setting registers gmidru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cech eptpc 1 grandmasteridentity field setting registers gmidrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cf0h eptpc 1 currentutcoffset/timesource field setting register cuotsr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4cf4h eptpc 1 stepsremoved field setting register srr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d00h eptpc 1 ptp-primary message destination mac address setting registers ppmacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d04h eptpc 1 ptp-primary message destination mac address setting registers ppmacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d08h eptpc 1 ptp-pdelay message mac address setting registers pdmacru 32 32 9 to 211 pclka 2 to 106 iclk eptpc table 4.1 list of i/o register s (address order) (60 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 132 of 230 jul 31, 2014 rx64m group 4. i/o registers 000c 4d0ch eptpc 1 ptp-pdelay message mac address setting registers pdmacrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d10h eptpc 1 ptp message ethertype setting register petyper 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d20h eptpc 1 ptp-primary message destination ip address setting register ppipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d24h eptpc 1 ptp-pdelay message destination ip address setting register pdipr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d28h eptpc 1 ptp event message tos setting register petosr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d2ch eptpc 1 ptp general message tos setting register pgtosr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d30h eptpc 1 ptp-primary message ttl setting register ppttlr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d34h eptpc 1 ptp-pdelay message ttl setting register pdttlr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d38h eptpc 1 ptp event message udp destination port number setting register peudpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d3ch eptpc 1 ptp general message udp destination port number setting register pgudpr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d40h eptpc 1 frame reception filter setting register ffltr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d60h eptpc 1 frame reception filter mac address 0 setting registers fmac0ru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d64h eptpc 1 frame reception filter mac address 0 setting registers fmac0rl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d68h eptpc 1 frame reception filter mac address 1 setting registers fmac1ru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4d6ch eptpc 1 frame reception filter mac address 1 setting registers fmac1rl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dc0h eptpc 1 asymmetric delay setting register dasymru 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dc4h eptpc 1 asymmetric delay setting register dasymrl 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dc8h eptpc 1 timestamp latency setting register tslatr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dcch eptpc 1 synfp operation setting register syconfr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dd0h eptpc 1 synfp frame format setting register syformr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000c 4dd4h eptpc 1 response message reception timeout register rstoutr 32 32 9 to 211 pclka 2 to 106 iclk eptpc 000d 0000h scifa8 serial mode register smr 16 16 3, 4 pclkb 2 iclk scifa 000d 0002h scifa8 bit rate register brr 8 8 3, 4 pclkb 2 iclk scifa 000d 0002h scifa8 modulation duty register mddr 8 8 3, 4 pclkb 2 iclk scifa 000d 0004h scifa8 serial control register scr 16 16 3, 4 pclkb 2 iclk scifa 000d 0006h scifa8 transmit fifo data register ftdr 8 8 3, 4 pclkb 2 iclk scifa 000d 0008h scifa8 serial status register fsr 16 16 3, 4 pclkb 2 iclk scifa 000d 000ah scifa8 receive fifo data register frdr 8 8 3, 4 pclkb 2 iclk scifa 000d 000ch scifa8 fifo control register fcr 16 16 3, 4 pclkb 2 iclk scifa 000d 000eh scifa8 fifo data count register fdr 16 16 3, 4 pclkb 2 iclk scifa 000d 0010h scifa8 serial port register sptr 16 16 3, 4 pclkb 2 iclk scifa 000d 0012h scifa8 line status register lsr 16 16 3, 4 pclkb 2 iclk scifa 000d 0014h scifa8 serial extended mode register semr 8 8 3, 4 pclkb 2 iclk scifa 000d 0016h scifa8 fifo trigger control register ftcr 16 16 3, 4 pclkb 2 iclk scifa 000d 0020h scifa9 serial mode register smr 16 16 3, 4 pclkb 2 iclk scifa 000d 0022h scifa9 bit rate register brr 8 8 3, 4 pclkb 2 iclk scifa 000d 0022h scifa9 modulation duty register mddr 8 8 3, 4 pclkb 2 iclk scifa 000d 0024h scifa9 serial control register scr 16 16 3, 4 pclkb 2 iclk scifa table 4.1 list of i/o register s (address order) (61 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 133 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0026h scifa9 transmit fifo data register ftdr 8 8 3, 4 pclkb 2 iclk scifa 000d 0028h scifa9 serial status register fsr 16 16 3, 4 pclkb 2 iclk scifa 000d 002ah scifa9 receive fifo data register frdr 8 8 3, 4 pclkb 2 iclk scifa 000d 002ch scifa9 fifo control register fcr 16 16 3, 4 pclkb 2 iclk scifa 000d 002eh scifa9 fifo data count register fdr 16 16 3, 4 pclkb 2 iclk scifa 000d 0030h scifa9 serial port register sptr 16 16 3, 4 pclkb 2 iclk scifa 000d 0032h scifa9 line status register lsr 16 16 3, 4 pclkb 2 iclk scifa 000d 0034h scifa9 serial extended mode register semr 8 8 3, 4 pclkb 2 iclk scifa 000d 0036h scifa9 fifo trigger control register ftcr 16 16 3, 4 pclkb 2 iclk scifa 000d 0040h scifa1 0 serial mode register smr 16 16 3, 4 pclkb 2 iclk scifa 000d 0042h scifa1 0 bit rate register brr 8 8 3, 4 pclkb 2 iclk scifa 000d 0042h scifa1 0 modulation duty register mddr 8 8 3, 4 pclkb 2 iclk scifa 000d 0044h scifa1 0 serial control register scr 16 16 3, 4 pclkb 2 iclk scifa 000d 0046h scifa1 0 transmit fifo data register ftdr 8 8 3, 4 pclkb 2 iclk scifa 000d 0048h scifa1 0 serial status register fsr 16 16 3, 4 pclkb 2 iclk scifa 000d 004ah scifa1 0 receive fifo data register frdr 8 8 3, 4 pclkb 2 iclk scifa 000d 004ch scifa1 0 fifo control register fcr 16 16 3, 4 pclkb 2 iclk scifa 000d 004eh scifa1 0 fifo data count register fdr 16 16 3, 4 pclkb 2 iclk scifa 000d 0050h scifa1 0 serial port register sptr 16 16 3, 4 pclkb 2 iclk scifa 000d 0052h scifa1 0 line status register lsr 16 16 3, 4 pclkb 2 iclk scifa 000d 0054h scifa1 0 serial extended mode register semr 8 8 3, 4 pclkb 2 iclk scifa 000d 0056h scifa1 0 fifo trigger control register ftcr 16 16 3, 4 pclkb 2 iclk scifa 000d 0060h scifa1 1 serial mode register smr 16 16 3, 4 pclkb 2 iclk scifa 000d 0062h scifa1 1 bit rate register brr 8 8 3, 4 pclkb 2 iclk scifa 000d 0062h scifa1 1 modulation duty register mddr 8 8 3, 4 pclkb 2 iclk scifa 000d 0064h scifa1 1 serial control register scr 16 16 3, 4 pclkb 2 iclk scifa 000d 0066h scifa1 1 transmit fifo data register ftdr 8 8 3, 4 pclkb 2 iclk scifa 000d 0068h scifa1 1 serial status register fsr 16 16 3, 4 pclkb 2 iclk scifa 000d 006ah scifa1 1 receive fifo data register frdr 8 8 3, 4 pclkb 2 iclk scifa 000d 006ch scifa1 1 fifo control register fcr 16 16 3, 4 pclkb 2 iclk scifa 000d 006eh scifa1 1 fifo data count register fdr 16 16 3, 4 pclkb 2 iclk scifa 000d 0070h scifa1 1 serial port register sptr 16 16 3, 4 pclkb 2 iclk scifa 000d 0072h scifa1 1 line status register lsr 16 16 3, 4 pclkb 2 iclk scifa 000d 0074h scifa1 1 serial extended mode register semr 8 8 3, 4 pclkb 2 iclk scifa 000d 0076h scifa1 1 fifo trigger control register ftcr 16 16 3, 4 pclkb 2 iclk scifa table 4.1 list of i/o register s (address order) (62 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 134 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0100h rspi0 rspi control register spcr 8 8 3, 4 pclkb 2 iclk rspia 000d 0101h rspi0 rspi slave select polarity register sslp 8 8 3, 4 pclkb 2 iclk rspia 000d 0102h rspi0 rspi pin control register sppcr 8 8 3, 4 pclkb 2 iclk rspia 000d 0103h rspi0 rspi status register spsr 8 8 3, 4 pclkb 2 iclk rspia 000d 0104h rspi0 rspi data register spdr 32 16, 32 3, 4 pclkb 2 iclk rspia 000d 0108h rspi0 rspi sequence control register spscr 8 8 3, 4 pclkb 2 iclk rspia 000d 0109h rspi0 rspi sequence status register spssr 8 8 3, 4 pclkb 2 iclk rspia 000d 010ah rspi0 rspi bit rate register spbr 8 8 3, 4 pclkb 2 iclk rspia 000d 010bh rspi0 rspi data control register spdcr 8 8 3, 4 pclkb 2 iclk rspia 000d 010ch rspi0 rspi clock delay register spckd 8 8 3, 4 pclkb 2 iclk rspia 000d 010dh rspi0 rspi slave select negation delay register sslnd 8 8 3, 4 pclkb 2 iclk rspia 000d 010eh rspi0 rspi next-access delay register spnd 8 8 3, 4 pclkb 2 iclk rspia 000d 010fh rspi0 rspi control register 2 spcr2 8 8 3, 4 pclkb 2 iclk rspia 000d 0110h rspi0 rspi command register 0 spcmd0 16 16 3, 4 pclkb 2 iclk rspia 000d 0112h rspi0 rspi command register 1 spcmd1 16 16 3, 4 pclkb 2 iclk rspia 000d 0114h rspi0 rspi command register 2 spcmd2 16 16 3, 4 pclkb 2 iclk rspia 000d 0116h rspi0 rspi command register 3 spcmd3 16 16 3, 4 pclkb 2 iclk rspia 000d 0118h rspi0 rspi command register 4 spcmd4 16 16 3, 4 pclkb 2 iclk rspia 000d 011ah rspi0 rspi command register 5 spcmd5 16 16 3, 4 pclkb 2 iclk rspia 000d 011ch rspi0 rspi command register 6 spcmd6 16 16 3, 4 pclkb 2 iclk rspia 000d 011eh rspi0 rspi command register 7 spcmd7 16 16 3, 4 pclkb 2 iclk rspia 000d 0400h usba system configuration control register syscfg 16 16 3, 4 pclkb 2 iclk usba 000d 0402h usba cpu bus wait register buswait 16 16 3, 4 pclkb 2 iclk usba 000d 0404h usba system configuration status register syssts0 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0406h usba pll status register pllsta 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0408h usba device state control register 0 dvstctr0 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0414h usba cfifo port register cfifo 32 8,16,32 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (63 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 135 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0418h usba d0fifo port register d0fifo 32 8,16,32 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 041ch usba d1fifo port register d1fifo 32 8,16,32 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0420h usba cfifo port select register cfifosel 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0422h usba cfifo port control register cfifoctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0428h usba d0fifo port select register d0fifosel 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 042ah usba d0fifo port control register d0fifoctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 042ch usba d1fifo port select register d1fifosel 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 042eh usba d1fifo port control register d1fifoctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0430h usba interrupt enable register 0 intenb0 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (64 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 136 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0432h usba interrupt enable register 1 intenb1 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0436h usba brdy interrupt enable register brdyenb 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0438h usba nrdy interrupt enable register nrdyenb 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 043ah usba bemp interrupt enable register bempenb 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 043ch usba sof output configuration register sofcfg 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 043eh usba phy setting register physet 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0440h usba interrupt status register 0 intsts0 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0442h usba interrupt status register 1 intsts1 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0446h usba brdy interrupt status register brdysts 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (65 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 137 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0448h usba nrdy interrupt status register nrdysts 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 044ah usba bemp interrupt status register bempsts 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 044ch usba frame number register frmnum 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 044eh usba frame number register ufrmnum 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0450h usba usb address register usbaddr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0454h usba usb request type register usbreq 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0456h usba usb request value register usbval 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0458h usba usb request index register usbindx 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 045ah usba usb request length register usbleng 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (66 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 138 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 045ch usba dcp configuration register dcpcfg 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 045eh usba dcp maximum packet size register dcpmaxp 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0460h usba dcp control register dcpctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0464h usba pipe window select register pipesel 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0468h usba pipe configuration register pipecfg 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 046ah usba pipe buffer register pipebuf 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 046ch usba pipe maximum packet size register pipemaxp 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 046eh usba pipe cycle control register pipeperi 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0470h usba pipe1 control register pipe1ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (67 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 139 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0472h usba pipe2 control register pipe2ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0474h usba pipe3 control register pipe3ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0476h usba pipe4 control register pipe4ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0478h usba pipe5 control register pipe5ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 047ah usba pipe6 control register pipe6ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 047ch usba pipe7 control register pipe7ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 047eh usba pipe8 control register pipe8ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0480h usba pipe9 control register pipe9ctr 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0490h usba pipe1 transaction counter enable register pipe1tre 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (68 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 140 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 0492h usba pipe1 transaction counter register pipe1trn 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0494h usba pipe2 transaction counter enable register pipe2tre 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0496h usba pipe2 transaction counter register pipe2trn 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0498h usba pipe3 transaction counter enable register pipe3tre 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 049ah usba pipe3 transaction counter register pipe3trn 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 049ch usba pipe4 transaction counter enable register pipe4tre 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 049eh usba pipe4 transaction counter register pipe4trn 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04a0h usba pipe5 transaction counter enable register pipe5tre 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04a2h usba pipe5 transaction counter register pipe5trn 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (69 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 141 of 230 jul 31, 2014 rx64m group 4. i/o registers 000d 04d0h usba device address 0 configuration register devadd0 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04d2h usba device address 1 configuration register devadd1 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04d4h usba device address 2 configuration register devadd2 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04d6h usba device address 3 configuration register devadd3 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04d8h usba device address 4 configuration register devadd4 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 04dah usba device address 5 configuration register devadd5 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0500h usba low power control register lpctrl 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0502h usba low power status register lpsts 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0540h usba battery charging control register bcctrl 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (70 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 142 of 230 jul 31, 2014 rx64m group 4. i/o registers note 1. when the same output trigger is specified for pulse ou tput groups 2 and 3 by the ppg0. pcr setting, the ppg0.ndrh address is 0008 81ech. when different output triggers are specified, the ppg0.ndrh addresses for pulse output groups 2 and 3 are 0008 81eeh and 0008 81ech, respectively. note 2. when the same output trigger is specified for pulse output groups 0 and 1 by the ppg0. pcr setting, the ppg0.ndrl address is 0008 81edh. when different output triggers are specified, the ppg0.ndrl addresses for pulse output groups 0 and 1 are 0008 81efh and 0008 81edh, respectively. note 3. when the same output trigger is specified for pulse ou tput groups 6 and 7 by the ppg1. pcr setting, the ppg1.ndrh address is 0008 81fch. when different output triggers are specified, the ppg1.ndrh addresses for pulse output groups 6 and 7 are 0008 81feh and 0008 81fch, respectively. note 4. when the same output trigger is specified for pulse output groups 4 and 5 by the ppg1. pcr setting, the ppg1.ndrl address is 0008 81fdh. when different output triggers are specified, the ppg1.ndrl addresses for pulse output groups 4 and 5 are 0008 81ffh and 0008 81fdh, respectively. note 5. when the register is accessed while the usb is operating, a delay may be generated in accessing. 000d 0544h usba function l1 control register 1 pl1ctrl1 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0546h usba function l1 control register 2 pl1ctrl2 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0548h usba host l1 control register 1 hl1ctrl1 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 054ah usba host l1 control register 2 hl1ctrl2 16 16 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0560h usba deep standby usb transceiver control/pin monitor register dpusr0r 32 32 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba 000d 0564h usba deep standby usb suspend/resume interrupt register dpusr1r 32 32 (3 + buswait) pclka or more rounded up to the nearest integer greater than 1 + (3 + buswait) (frequency ratio of iclk/ pclkb)* 5 usba table 4.1 list of i/o register s (address order) (71 / 71) address module symbol register name register symbol number of bits access size number of access cycles related function iclk ?? pclk iclk ? pclk
r01ds0173ej0100 rev.1.00 page 143 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. ports 07, 11 to 17, 20, 21, 30 to 33, 67, and c0 to c3 are 5 v tolerant. note 2. connect the avcc0, avcc1, and vcc_usb pins to vcc, and the avss0, avss1, and vss_usb pins to vss. when the a/d converter unit 0 is not to be used, connect the vrefh0 pin to vcc and th e vrefl0 pin to vss, respectively. do not leave these pins open. when the usba is not to be used, connect the vcc_usba and avcc_usba pins to vcc and the vss1_usba, vss2_usba, pvss_usba, and avss_usba pins to vss, res pectively. do not l eave these pins open. table 5.1 absolute maximum rating conditions: vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v item symbol value unit power supply voltage vcc, vcc_usb ?0.3 to +4.6 v v batt power supply voltage v batt ?0.3 to +4.6 v input voltage (except for ports for 5 v tolerant* 1 )v in ?0.3 to vcc + 0.3 v input voltage (ports for 5 v tolerant* 1 )v in ?0.3 to +5.8 v reference power supply voltage vrefh0 ?0.3 to vcc + 0.3 v analog power supply voltage avcc0, avcc1* 2 ?0.3 to +4.6 v usba power supply voltage vcc_usba* 2 ?0.3 to +4.6 v usba analog power supply voltage avcc_usba* 2 ?0.3 to +4.6 v analog input voltage v an ?0.3 to avcc + 0.3 v operating temperature t opr ?40 to +85 c operating temperature (high-temperature products) t opr ?40 to +105 (under planning) c storage temperature t stg ?55 to +125 c
r01ds0173ej0100 rev.1.00 page 144 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.2 dc characteristics note 1. this does not include the pins, which are multiplexed as ports for 5 v tolerant. note 2. ports 07, 11 to 17, 20, 21, 30 to 33, 67, and c0 to c3 are 5 v tolerant. note 3. for p32, p31, and p30, input as follows when the v batt power supply is selected. vih min. = v batt 0.8, vih max. = v batt + 0.3, vil min. = ?0.3, vil max. = v batt 0.2 (v batt = 2.0 to 3.6 v) table 5.2 dc characteristics (1) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions schmitt trigger input voltage irq input pin* 1 mtu input pin* 1 gpt input pin* 1 poe3 input pin* 1 tpu input pin* 1 tmr input pin* 1 sci input pin* 1 adtrg# input pin* 1 res#, nmi v ih vcc 0.8 ? vcc + 0.3 v v il ?0.3 ? vcc 0.2 ? v t vcc 0.06 ? ? riic input pin (except for smbus) v ih vcc 0.7 ? 5.8 v il ?0.3 ? vcc 0.3 ? v t vcc 0.05 ? ? ports for 5 v tolerant* 2 v ih vcc 0.8 ? 5.8 v il ?0.3 ? vcc 0.2 other input pins excluding ports for 5 v tolerant* 3 v ih vcc 0.8 ? vcc + 0.3 v il ?0.3 ? vcc 0.2 input high voltage (except for schmitt trigger input pin) md pin, emle v ih vcc 0.9 ? vcc + 0.3 v extal, rspi input pin, exdmac input pin, wait#, tck, ssi input pin, sdhi input pin, mmc input pin, pdc input pin, qspi input pin vcc 0.8 ? vcc + 0.3 etherc input pin 2.3 ? vcc + 0.3 xcin ? ? vcc + 0.3 d0 to d31 vcc 0.7 ? vcc + 0.3 riic (smbus) 2.1 ? 5.8 input low voltage (except for schmitt trigger input pin) md pin, emle v il ?0.3 ? vcc 0.1 v extal, rspi input pin, etherc input pin, exdmac input pin, wait#, tck, ssi input pin, sdhi input pin, mmc input pin, pdc input pin, qspi input pin ?0.3 ? vcc 0.2 xcin ?0.3 ? ? d0 to d31 ?0.3 ? vcc 0.3 riic (smbus) ?0.3 ? 0.8
r01ds0173ej0100 rev.1.00 page 145 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. the input leakage current value at the emle and bscanp pins are only when v in = 0 v. table 5.3 dc characteristics (2) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t op r item symbol min. typ. max. unit test conditions output high voltage all output pins v oh vcc ? 0.5 ? ? v i oh = ?1 ma output low voltage all output pins (except for riic pins and etherc output pin) v ol ??0.5vi ol = 1.0 ma riic output pin ? ? 0.4 i ol = 3.0 ma ??0.6 i ol = 6.0 ma riic output pin (only p12 and p13 in channel 0) v ol ??0.4vi ol = 15.0 ma (icfer.fmpe = 1) ?0.4? i ol = 20.0 ma (icfer.fmpe = 1) etherc output pin v ol ??0.4vi ol = 1.0 ma input leakage current res#, md pin, emle* 1 , bscanp* 1 , nmi ? i in ? ??1.0 av in = 0 v v in = vcc three-state leakage current (off state) other than ports for 5 v tolerant ? i tsi ? ??1.0 av in = 0 v v in = vcc ports for 5 v tolerant ? ? 5.0 v in = 0 v v in = 5.5 v input pull-up mos current ports 0 to 2, 3, 4 to g, j3, j5 i p ?300 ? ?10 a vcc = 2.7 to 3.6 v v in = 0 v input pull-down mos current emle, bscanp i p 10 ? 300 av in = vcc input capacitance all input pins (except for ports 03, 05, 12, 13, 16, 17, emle, bscanp, usb0_dp, usb0_dm, usba_dp, and usba_dm) c in ? ? 8 pf vbias = 0 v vamp = 20 mv f = 1 mhz t a = 25c ports 03, 05, 12, 13, 16, 17, emle, bscanp, usb0_dp, usb0_dm, usba_dp, and usba_dm ??16
r01ds0173ej0100 rev.1.00 page 146 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. supply current values are with all output pi ns unloaded and all input pull-up moss in the off state. note 2. supply of the clock signal to peripheral modules is stopped in this state. this does not include operations as bgo (back ground operations). note 3. i cc depends on f (iclk) as follows. (iclk/pclka:pclkb/pclkc/pclkd:bclk:bclk pin = 10:5:10:5 when extal = 12 mhz) i cc max. = 0.77 f + 18 (max. operation in high-speed operating mode) i cc typ. = 0.08 f + 6 (normal operation in high-speed operating mode) i cc typ. = 0.5 f + 2.6 (low-speed operating mode 1) i cc max. = 0.36 f + 18 (sleep mode) note 4. this does not include operations as bgo (background operati ons). whether supply of the clock signal to peripheral module s continues or is stopped only depends on the state determined by the settings of the bits in module stop control registers a to d. the setting for the peripheral module cloc k stopped state is fclk = bclk = pclka = pclkb = pclkc = pclkd = bclk pin = 3.75 mhz (division by 64). note 5. this is the increase for programming or erasure of the c ode flash memory (limit ations apply to the combinations of range s in which writing proceed) or data flash memory duri ng program execution in the code flash memory. note 6. the low power consumption func tion is disabled and deepcut[1:0] = 01b. note 7. the low power consumption f unction is enabled and deepcut[1:0] = 11b. table 5.4 dc characteristics (3) conditions: vcc = avcc0 = avcc1 = vrefh0 = vcc_usb = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions supply current* 1 high-speed operating mode max.* 2 i cc * 3 ? ? 110 ma iclk = 120 mhz pclka = 120 mhz pclkb = 60 mhz pclkc = 60 mhz pclkd = 60 mhz fclk = 60 mhz bclk = 120 mhz bclk pin = 60 mhz normal peripheral function clock signal supplied* 4 ?39 ? peripheral function clock signal stopped* 4 ?16 ? coremark peripheral function clock signal stopped* 4 ?21 ? sleep mode: supply of the clock signal to peripheral modules is stopped* 4 32 61 all-module-clock-stop mode (reference value) ? 10 28 increased by bgo operation *5 reading from the code flash memory while the data flash memory is being programmed ?7 ? reading from the code flash memory while the code flash memory is being programmed ?10 ? low-speed operating mode 1: supply of the clock signal to peripheral modules is stopped* 4 ? 3 ? all clocks 1 mhz low-speed operating mode 2: supply of the clock signal to peripheral modules is stopped* 4 ? 1.2 ? all clocks 32.768 khz software standby mode ? 0.7 10 deep software standby mode power supplied to standby ram and usb resume detecting unit (usb0 only) ?22 63 a power not supplied to standby ram and usb resume detecting unit (usb0 only) power-on reset circuit and low- power consumption function disabled* 6 ? 12.5 26 power-on reset circuit and low- power consumption function enabled* 7 ? 3.1 13.5 increased by rtc operation when a crystal oscillator for low clock loads is in use ?0.6 ? when a crystal oscillator for standard clock loads is in use ?2.0 ? rtc operating while vcc is off (with the battery backup function, only the rtc and sub-clock oscillator operate) when a crystal oscillator for low clock loads is in use ?0.9 ? v batt = 2.0 v, vcc = 0 v ?1.6 ? v batt = 3.3 v, vcc = 0 v when a crystal oscillator for standard clock loads is in use ?1.7 ? v batt = 2.0 v, vcc = 0 v ?3.3 ? v batt = 3.3 v, vcc = 0 v
r01ds0173ej0100 rev.1.00 page 147 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. the reference power supply current is included in the power supply current value for 12-bit a/d conversion (unit 1) and d/a conversion. note 2. this applies when v batt is used. table 5.5 dc characteristics (4) conditions: vcc = avcc0 = avcc1 = vrefh0 = vcc_usb = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions analog power supply current* 1 during 12-bit a/d conversion (unit 0) ai cc ? 0.7 1.0 ma iavcc0_ad during 12-bit a/d conversion (unit 0) with the channel-dedicated sample-and-hold circuits for 3 channels operating ? 1.7 2.5 ma iavcc0_ad+sh during 12-bit a/d conversion (unit 1) ? 0.6 1.0 ma iavcc1_ad during 12-bit a/d conversion (unit 1) with the temperature sensor operating ? 0.7 1.1 ma iavcc1_ad+temp during d/a conversion (per unit) without amp output ? 0.24 0.4 ma iavcc1_da with amp output ? 0.4 0.7 ma waiting for a/d, d/a, or temperature sensor conversion (all units) ? 0.9 1.4 ma iavcc0 + iavcc1 a/d, d/a converter, temperature sensor in standby mode (all units) ?1.33.0 a iavcc0 + iavcc1 reference power supply current during 12-bit a/d conversion (unit 0) ai refh ? 70 120 a ivrefh0 waiting for 12-bit a/d conversion (unit 0) ? 0.07 0.4 a ivrefh0 12-bit a/d converter in standby mode (unit 0) ? 0.07 0.2 a ivrefh0 usb operating current low speed usb0 i ccusbls ? 3.5 6.5 ma vcc_usb usba ? 8.5 12.0 ma vcc_usba = avcc_usba (physet.hseb = 0) usba ? 2.8 3.6 ma vcc_usba = avcc_usba (physet.hseb = 1) full speed usb0 i ccusbfs ? 4.0 10.0 ma vcc_usb usba ? 12.0 20.0 ma vcc_usba = avcc_usba (physet.hseb = 0) usba ? 6.5 13.0 ma vcc_usba = avcc_usba (physet.hseb = 1) standby mode (direct power down) usba i ccusbsby ?0.13.0 a vcc_usba = avcc_usba ram standby voltage v ram 2.7 ? ? v vcc rising gradient srvcc 8.4 ? 20000 s/v vcc falling gradient* 2 sfvcc 8.4 ? ? s/v
r01ds0173ej0100 rev.1.00 page 148 of 230 jul 31, 2014 rx64m group 5. electrical characteristics caution: to protect the lsi?s reliability, the output current values should not exceed the values in this table. note 1. this is the value when normal dr iving ability is set with a pin for which normal driv ing ability is selectable. note 2. this is the value when high driving ability is set with a pin for which normal driving ability is selectable or the valu e of the pin to which high driving ability is fixed. table 5.6 permissible output currents conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit permissible output low current (average value per pin) all output pins* 1 normal drive i ol ??2.0ma all output pins* 2 high drive i ol ??3.8ma permissible output low current (max. value per pin) all output pins* 1 normal drive i ol ??4.0ma all output pins* 2 high drive i ol ??7.6ma permissible output low current (total) total of all output pins ? i ol ??80ma permissible output high current (average value per pin) all output pins* 1 normal drive i oh ? ? ?2.0 ma usb_dpupe pin* 2 high drive i oh ? ? ?3.8 ma permissible output high current (max. value per pin) all output pins* 1 normal drive i oh ? ? ?4.0 ma all output pins* 2 high drive i oh ? ? ?7.6 ma permissible output high current (total) total of all output pins ? i oh ???80ma
r01ds0173ej0100 rev.1.00 page 149 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3 ac characteristics note 1. the fclk must run at a frequency of at l east 4 mhz when changing the flash memory contents. note 1. when the 12-bit a/d converter is used, the frequency must be set to at least 1 mhz. table 5.7 operating frequency (high-speed operating mode) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t op r item symbol min. typ. max. unit operating frequency system clock (iclk) f ? ? 120 mhz peripheral module clock (pclka) ? ? 120 peripheral module clock (pclkb) ? ? 60 peripheral module clock (pclkc) ? ? 60 peripheral module clock (pclkd) ? ? 60 flash-if clock (fclk) ? * 1 ?60 external bus clock (bclk) packages with 177 to 144 pins only ??120 package with 100 pins only ? ? 60 bclk pin output packages with 177 to 144 pins only ??60 package with 100 pins only ? ? 30 sdram clock (sdclk) packages with 177 to 144 pins only ??60 sdclk pin output packages with 177 to 144 pins only ??60 table 5.8 operating frequency (low-speed operating mode 1) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit operating frequency system clock (iclk) f ? ? 1 mhz peripheral module clock (pclka) ? ? 1 peripheral module clock (pclkb) ? ? 1 peripheral module clock (pclkc)* 1 ?? 1 peripheral module clock (pclkd)* 1 ?? 1 flash-if clock (fclk) ? ? 1 external bus clock (bclk) packages with 177 to 144 pins only ?? 1 package with 100 pins only ? ? 1 bclk pin output packages with 177 to 144 pins only ?? 1 package with 100 pins only ? ? 1 sdram clock (sdclk) packages with 177 to 144 pins only ?? 1 sdclk pin output packages with 177 to 144 pins only ?? 1
r01ds0173ej0100 rev.1.00 page 150 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. the 12-bit a/d converter cannot be used. table 5.9 operating frequency (low-speed operating mode 2) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit operating frequency system clock (iclk) f 32 ? 264 khz peripheral module clock (pclka) ? ? 264 peripheral module clock (pclkb) ? ? 264 peripheral module clock (pclkc)* 1 ??264 peripheral module clock (pclkd)* 1 ??264 flash-if clock (fclk) 32 ? 264 external bus clock (bclk) packages with 177 to 144 pins only ??264 package with 100 pins only ? ? 264 bclk pin output packages with 177 to 144 pins only ??264 package with 100 pins only ? ? 264 sdram clock (sdclk) packages with 177 to 144 pins only ??264 sdclk pin output packages with 177 to 144 pins only ??264
r01ds0173ej0100 rev.1.00 page 151 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.1 reset timing figure 5.1 reset input timing at power-on figure 5.2 reset input timing table 5.10 reset timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp 1 ? ? ms figure 5.1 deep software standby mode t reswd 0.6 ? ? ms figure 5.2 software standby mode, low-speed operating mode 2 t resws 0.3 ? ? ms programming or erasure of the code flash memory, or programming, erasure or blank checking of the data flash memory t reswf 200 ? ? s other than above t resw 200 ? ? s waiting time after release from the res# pin reset t reswt 62 ? 63 t lcyc figure 5.1 internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 108 ? 116 t lcyc vcc res# internal reset signal (low is valid) t reswp t reswt res# internal reset signal (low is valid) t reswd , t resws , t reswf , t resw t reswt
r01ds0173ej0100 rev.1.00 page 152 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.2 clock timing figure 5.3 bclk pin and sdclk pin output timing table 5.11 bclk pin output, sdclk pin output clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions bclk pin output cycle ti me packages with 177 to 144 pins t bcyc 16.6 ? ? ns figure 5.3 packages with 100 pins or less 33.2 ? ? ns bclk pin output high pulse width t ch 3.3 ? ? ns bclk pin output low pulse width t cl 3.3 ? ? ns bclk pin output rising time t cr ?? 5ns bclk pin output falling time t cf ?? 5ns sdclk pin output cycle time packages with 177 to 144 pins t bcyc 16.6 ? ? ns sdclk pin output high pulse width t ch 3.3 ? ? ns sdclk pin output low pulse width t cl 3.3 ? ? ns sdclk pin output rising time t cr ?? 5ns sdclk pin output falling time t cf ?? 5ns t cf t ch t bcyc , t sdcyc t cr t cl bclk pin output, sdclk pin output test conditions: voh = vcc 0.7, vol = vcc 0.3, c = 30 pf
r01ds0173ej0100 rev.1.00 page 153 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.4 extal external clock input timing note 1. when using a main clock, ask the manufacturer of the osci llator to evaluate its oscillation. refer to the results of eva luation provided by the manufacturer for t he oscillation st abilization time. note 2. the number of cycles selected by the value of the mo scwtcr.msts[7:0] bits determines the main clo ck oscillation stabilization wait time in ac cord with the formula below. t mainoscwt = [(msts[7:0] bits 32) + 10] / f loco figure 5.5 main clock oscillation start timing table 5.12 extal clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions extal external clock input cycle time t excyc 41.66 ? ? ns figure 5.4 extal external clock input high pulse width t exh 15.83 ? ? ns extal external clock input low pulse width t exl 15.83 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns table 5.13 main clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions main clock oscillation frequency f main 8?24mhz main clock oscillator stab ilization time (crystal) t mainosc ???* 1 ms figure 5.5 main clock oscillation stabili zation wait time (crystal) t mainoscwt ???* 2 ms t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillator output mosccr.mostp t mainosc main clock t mainoscwt oscovfsr.moovf
r01ds0173ej0100 rev.1.00 page 154 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.6 loco clock oscillation start timing figure 5.7 iwdt-dedicated low-speed clock oscillation start timing table 5.14 loco and iwdt-dedicated low-speed clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions loco clock cycle time t lcyc 4.63 4.16 3.78 s loco clock oscillation frequency f loco 216 240 264 khz loco clock oscillation stabilization wait time t locowt ??44 s figure 5.6 iwdt-dedicated low-speed clock cycle time t ilcyc 9.26 8.33 7.57 s iwdt-dedicated low-speed cl ock oscillation frequency f iloco 108 120 132 khz iwdt-dedicated low-speed clock os cillation stabi lization wait time t ilocowt ? 142 190 s figure 5.7 loco clock lococr.lcstp t locowt on-chip oscillator output oscovfsr.ilcovf ilococr.ilcstp t ilocowt iwdt-dedicated low-speed clock iwdt-dedicated on-chip oscillator output
r01ds0173ej0100 rev.1.00 page 155 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.8 hoco clock oscillation start timi ng (oscillation is st arted by setting the hococr.hcstp bit) figure 5.9 high-speed on-chip oscillator power supply control timing table 5.15 clock timing (ex cept for sub-clock related) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions hoco clock oscillation frequency f hoco 15.61 16 16.39 mhz -20 ? c ??? ta ??? 85 ? c 17.56 18 18.44 mhz 19.52 20 20.48 mhz 15.52 16 16.48 mhz -40 ? c ? t a ? -20 ? c 17.46 18 18.54 mhz 19.40 20 20.60 mhz hoco clock oscillation stabilization wait time t hocowt ? 105 149 s figure 5.8 hoco clock power supply stabilization time t hocop ??150 s figure 5.9 hoco clock hococr.hcstp oscovfsr.hcovf t hocowt high-speed on-chip oscillator output internal power supply for high-speed on-chip oscillator hocopcr.hocopcnt t hocop hococr.hcstp
r01ds0173ej0100 rev.1.00 page 156 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.10 pll clock os cillation start timing note 1. when using a sub-clock, ask the manuf acturer of the oscillator to evaluate its oscillation. refer to the results of eval uation provided by the manufacturer for t he oscillation stabilization time. note 2. the number of cycles selected by the value of the soscwtcr.ssts[7:0] bits determines the sub-cl ock oscillation stabilization wait time in accord with the formula below. t suboscwt = [(ssts[7:0] bits 16384) + 10] / f loco figure 5.11 sub-clock oscillation start timing table 5.16 pll clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions pll clock oscillation frequency f pll 120 ? 240 mhz pll clock oscillation stabilization wait time t pllwt ? 259 320 s figure 5.10 table 5.17 sub-clock timing conditions: vcc = avcc0 = avcc1 = vcc_usb = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, v batt = 2.0 to 3.6 v, t a = t opr item symbol min. typ. max. unit test conditions sub-clock oscillation frequency f sub ? 32.768 ? khz sub-clock oscillation stabilization time t subosc ??* 1 s figure 5.11 sub-clock oscillation stabilization wait time t suboscwt ??* 2 s pllcr2.pllen oscovfsr.plovf pll clock t pllwt pll circuit output sub-clock oscillator output sosccr.sostp t subosc sub-clock oscovfsr.soovf t suboscwt
r01ds0173ej0100 rev.1.00 page 157 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the time for return after release from software standby is determined by the value obt ained by adding the oscillation st abilization waiting time (t sbyoscwto ) and the time required for operations by t he software standby release sequencer (t sbyseq ). note 2. when several oscillators were running before the transiti on to software standby, the greatest value of the oscillation s tabilization waiting time t sbyoscwt is selected. note 3. for n, the greatest value is selected fr om among the internal clock division settings. note 4. this condition applies when f iclk :f fclk = 1:1, 2:1, or 4:1. table 5.18 timing of recovery from low power consumption modes (1) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions t sbyoscwt * 2 t sbyseq * 3 recovery time after cancellation of software standby mode* 1 crystal resonator connected to main clock oscillator main clock oscillator operating t sbymc ? ? {( msts[7:0] bits 32 ) + 76 } / 0.216 100 s + 7/f iclk + 2n/f main s figure 5.12 main clock oscillator and pll circuit operating t sbypc {( msts[7:0] bits 32 ) + 138 } / 0.216 100 s + 7/f iclk + 2n/f pll external clock input to main clock oscillator main clock oscillator operating t sbyex 352 100 s + 7/f iclk + 2n/f exmain main clock oscillator and pll circuit operating t sbype 639 100 s + 7/f iclk + 2n/f pll sub-clock oscillator operating t sbysc {( ssts[7:0] bits 16384 ) + 13 } / 0.216 + 10/f fclk 100 s + 4/f iclk + 2n/f sub high-speed on-chip oscillator operating high-speed on-chip oscillator operating t sbyho 454 100 s + 7/f iclk + 2n/f hoco high-speed on-chip oscillator operating and pll circuit operating t sbyph 741 100 s + 7/f iclk + 2n/f pll low-speed on-chip oscillator operating* 4 t sbylo 338 100 s + 7/f iclk + 2n/f loco
r01ds0173ej0100 rev.1.00 page 158 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.12 software standby mode cancellation timing oscillator (system clock) iclk irq software standby mode t sbymc, t sbyex, t sbypc, t sbype, t sbyph, t sbysc, t sbyho, t sbylo oscillator (other than the system clock) t sbyoscwt t sbyseq oscillator (system clock) iclk irq software standby mode t sbymc, t sbyex, t sbypc, t sbype, t sbyph, t sbysc, t sbyho, t sbylo t sbyoscwt t sbyoscwt when stabilization of the system clock oscillator is slower t sbyseq oscillator (other than the system clock) when stabilization of an oscillator ot her than the system clock is slower
r01ds0173ej0100 rev.1.00 page 159 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.13 deep software standby mode cancellation timing table 5.19 timing of recovery from low power consumption modes (2) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min typ max unit test conditions recovery time after cancellation of deep software standby mode t dsby ? ? 0.9 ms figure 5.13 wait time after cancellation of deep software standby mode t dsbywt 31 ? 32 t lcyc oscillator irq internal reset (low is valid) reset exception handling start deep software standby mode deep software standby reset (low is valid) t dsby t dsbywt
r01ds0173ej0100 rev.1.00 page 160 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.4 control signal timing note 1. t pbcyc : pclkb cycle figure 5.14 nmi interrupt input timing figure 5.15 irq interrupt input timing table 5.20 control signal timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, plckb = 8 to 60 mhz, t a = t opr item symbol min.* 1 typ. max. unit test conditions* 1 nmi pulse width t nmiw 200 ? ? ns t pbcyc 2 200 ns, figure 5.14 t pbcyc 2 ? ? ns t pbcyc 2 > 200 ns, figure 5.14 irq pulse width t irqw 200 ? ? ns t pbcyc 2 200 ns, figure 5.15 t pbcyc 2 ? ? ns t pbcyc 2 > 200 ns, figure 5.15 nmi t nmiw irq t irqw
r01ds0173ej0100 rev.1.00 page 161 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.5 bus timing table 5.21 bus timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, iclk = pclka = 8 to 120 mhz, pclkb = bclk = sdclk = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit test conditions address delay time t ad ? 12.5 ns figure 5.16 to figure 5.21 byte control delay time t bcd ? 12.5 ns cs# delay time t csd ? 12.5 ns ale delay time t aled ? 12.5 ns rd# delay time t rsd ? 12.5 ns read data setup time t rds 12.5 ? ns read data hold time t rdh 0?ns wr# delay time t wrd ? 12.5 ns write data delay time t wdd ? 12.5 ns write data hold time t wdh 0?ns wait# setup time t wts 12.5 ? ns figure 5.22 wait# hold time t wth 0?ns address delay time 2 (sdram) t ad2 1 12.5 ns figure 5.23 cs# delay time 2 (sdram) t csd2 1 12.5 ns dqm delay time (sdram) t dqmd 1 12.5 ns cke delay time (sdram) t cked 1 12.5 ns read data setup time 2 (sdram) t rds2 10 ? ns read data hold time 2 (sdram) t rdh2 0?ns write data delay time 2 (sdram) t wdd2 ? 12.5 ns write data hold time 2 (sdram) t wdh2 1?ns we# delay time (sdram) t wed 1 12.5 ns ras# delay time (sdram) t rasd 1 12.5 ns cas# delay time (sdram) t casd 1 12.5 ns
r01ds0173ej0100 rev.1.00 page 162 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.16 address/data multiplexed bus read access timing figure 5.17 address/data multiplexed bus write access timing address bus/ data bus data read (rd#) t ad bclk address bus address latch (ale) chip select (cs1#) t aled t w1 t w2 t n1 t ad t ad t rds t n2 t rsd t rsd t w3 t w4 t w5 t end t a1 t a1 t an address cycle data cycle t rdh t aled t csd t csd address bus/ data bus data write (wrm#) t ad bclk address bus address latch (ale) chip select (cs1#) t aled t w1 t w2 t n1 t ad t ad t n2 t wrd t wrd t w3 t w4 t w5 t end t a1 t a1 t an address cycle data cycle t aled t csd t csd t wdd t wdh t n3
r01ds0173ej0100 rev.1.00 page 163 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.18 external bus timing/normal read cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d31 to d0 (read) byte strobe mode 1-write strobe mode bc3# to bc0# common to both byte strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t bcd t w1 t w2 t end t n1 t n2 rdon:1 csrwait:2 csroff:2 cson:0
r01ds0173ej0100 rev.1.00 page 164 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.19 external bus timing/normal write cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte strobe mode 1-write strobe mode bc3# to bc0# common to both byte strobe mode and 1-write strobe mode t bcd t csd t csd t ad t ad t ad t bcd d31 to d0 (write) wr3# to wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t n2 wron:1 wdon:1* 1 cswwait:2 wdoff:1* 1 cson:0 cswoff:2 note 1. be sure to specify wdon and wdoff as at least one cycle of bclk.
r01ds0173ej0100 rev.1.00 page 165 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.20 external bus timing/page read cycle (bus clock synchronized) figure 5.21 external bus timing/page write cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d31 to d0 (read) byte strobe mode 1-write strobe mode bc3# to bc0# common to both byte strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t rdh t rds t ad t bcd t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t n2 t ad t ad t ad t ad rdon:1 csrwait:2 csroff:2 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte strobe mode 1-write strobe mode bc3# to bc0# common to both byte strobe mode and 1-write strobe mode t bcd t csd t csd t ad t bcd t w1 d31 to d0 (write) wr3# to wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t n2 t dw1 t ad t ad t ad t ad wron:1 wdon:1* 1 cswwait:2 cspwwait:2 wdoff:1* 1 cspwwait:2 wdoff:1* 1 wdoff:1* 1 cson:0 note 1. be sure to specify wdon and wdoff as at least one cycle of bclk. wron:1 wdon:1* 1 wron:1 wdon:1* 1 cswoff:2
r01ds0173ej0100 rev.1.00 page 166 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.22 external bus timing/external wait control t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs7# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t n2 external wait
r01ds0173ej0100 rev.1.00 page 167 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.23 sdram space single read bus timing t ad2 sdclk pin a18 to a0 sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke t dqmd (high) row address column address sdram command act rd pra t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t wed t wed t csd2 t csd2 t casd t casd t rds2 t rdh2 pra command note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 168 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.24 sdram space single write bus timing t ad2 sdclk pin a18 to a0 sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke t dqmd (high) row address column address sdram command act wr pra t ad2 t csd2 t rasd t wed t casd t wdd2 t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t csd2 t csd2 t casd t wed t wed t wed t wdh2 pra command note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 169 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.25 sdram space mu ltiple read bus timing sdclk pin act rd rd rd rd pra a18 to a0 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 ap * 1 sdcs# ras# cas# we# cke dqmn d31 to d0 c1 c2 c3 row address c0 (column address) t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t rasd t casd t casd t casd t wed t wed (high) t dqmd t dqmd t rds2 t rdh2 t rds2 t rdh2 pra command note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 170 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.26 sdram space mu ltiple write bus timing act wr pra wr wr wr sdclk pin a18 to a0 ap* 1 sdcs# ras# cas# we# cke dqmn d31 to d0 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t rasd t casd t casd t casd t wed t wed (high) t dqmd t dqmd t wdd2 t wdh2 t wdd2 t wdh2 c1 c2 c3 row address c0 (column address) pra command note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 171 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.27 sdram space multiple read line stride bus timing r1 a18 to a0 sdclk pin sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke sdram command act rd rd rd rd pra act rd rd rd rd pra t casd t rasd t csd2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t rasd t casd t casd t rasd t rasd t casd t dqmd t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 (high) row address c0 (column address 0) c1 c2 c3 c4 c5 c6 c7 pra command pra command t wed t wed t wed t wed note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 172 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.28 sdram space mode register set bus timing a18 to a0 sdclk pin sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke sdram command (hi-z) (high) t casd t rasd t csd2 t ad2 mrs t ad2 t ad2 t ad2 t casd t rasd t csd2 t wed t wed note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 173 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.29 sdram space self-refresh bus timing a18 to a0 (rfs) sdclk pin sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke (hi-z) t cked (high) t casd t casd t casd t rasd t rasd t rasd t csd2 t csd2 t csd2 t ad2 t ad2 (rfa) ts (rfx) (rfa) t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t casd t casd t casd t casd t cked sdram command t dqmd t dqmd note 1. address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01ds0173ej0100 rev.1.00 page 174 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.6 exdmac timing figure 5.30 edreq0 and edreq1 input timing figure 5.31 edack0 and edack1 single-address transfer timing (for a cs area) table 5.22 exdmac timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, iclk = pclka = 8 to 120 mhz, pclkb = bclk = sdclk = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit test conditions exdmac edreq setup time t edrqs 13 ? ns figure 5.30 edreq hold time t edrqh 2?ns edack delay time t edacd ? 13 ns figure 5.31, figure 5.32 bclk pin t edrqs t edrqh edreq0, edreq1 edack0, edack1 t edacd bclk pin t edacd
r01ds0173ej0100 rev.1.00 page 175 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.32 edack0 and edack1 single-a ddress transfer timing (for sdram) edack0, edack1 t edacd bclk pin t edacd
r01ds0173ej0100 rev.1.00 page 176 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.3.7 timing of on-chi p peripheral modules note 1. t pbcyc : pclkb cycle figure 5.33 i/o port input timing table 5.23 i/o port timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pbcyc figure 5.33 port pclkb t prw
r01ds0173ej0100 rev.1.00 page 177 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.34 tpu input capture input timing figure 5.35 tpu clock input timing table 5.24 tpu timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions tpu input capture input pulse width single-edge setting t ticw 1.5 ? t pbcyc figure 5.34 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pbcyc figure 5.35 both-edge setting 2.5 ? phase counting mode 2.5 ? input capture input pclkb t ticw tclka to tclkh pclkb t tckwl t tckwh
r01ds0173ej0100 rev.1.00 page 178 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.36 tmr clock input timing note 1. t pbcyc : pclkb cycle figure 5.37 cmtw input capture input timing table 5.25 tmr timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions tmr timer clock pulse width single-edge setting t tmcwh, t tmcwl 1.5 ? t pbcyc figure 5.36 both-edge setting 2.5 ? table 5.26 cmtw timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions cmtw input capture input pulse width single-edge setting t cmtwticw 1.5 ? t pbcyc figure 5.37 both-edge setting 2.5 ? pclkb tmci0 to tmci3 t tmcwl t tmcwh input capture input pclkb t cmtwicw
r01ds0173ej0100 rev.1.00 page 179 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pacyc : pclka cycle figure 5.38 mtu3 input capture input timing figure 5.39 mtu3 clock input timing table 5.27 mtu3 timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions mtu3 input capture input pulse width single-edge setting t mticw 1.5 ? t pacyc figure 5.38 both-edge setting 2.5 ? timer clock pulse width single-edge setting t mtckwh, t mtckwl 1.5 ? t pacyc figure 5.39 both-edge setting 2.5 ? phase counting mode 2.5 ? input capture input pclka t mticw mtclka to mtclkd pclka t mtckwl t mtckwh
r01ds0173ej0100 rev.1.00 page 180 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.40 poe# input timing table 5.28 poe3 timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions poe poe# input pulse width t poew 1.5 ? t pbcyc figure 5.40 poen# input pclkb t poew
r01ds0173ej0100 rev.1.00 page 181 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pacyc : pclka cycle figure 5.41 gpt input capture input timing figure 5.42 gpt external trigger input timing table 5.29 gpt timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions gpt input capture input pulse width single-edge setting t gticw 3?t pacyc figure 5.41 both-edge setting 5? external trigger input pulse width single-edge setting t otetw 1.5 ? t pacyc figure 5.42 both-edge setting 2.5 ? input capture input pclka t gticw external trigger pclka t gtew
r01ds0173ej0100 rev.1.00 page 182 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.43 a/d converter trigger input timing note 1. t pbcyc : pclkb cycle note 2. t cac : cac count clock source cycle table 5.30 a/d converter trigger timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions a/d converter a/d converter trigger input pulse width t trgw 1.5 ? t pbcyc figure 5.43 table 5.31 cac timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item* 1, * 2 symbol min.* 1 max. unit* 1 test conditions cac cacref input pulse width t pbcyc t cac t cacref 4.5t cac + 3t pbcyc ?ns t pbcyc > t cac 5t cac + 6.5t pbcyc ? adtrg0#, adtrg1# pclkb t trgw
r01ds0173ej0100 rev.1.00 page 183 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle; t pacyc : pclka cycle note 2. when the semr.abcs and semr.bgdm bits are set to 1 note 3. when the semr.abcs0 and semr.bgdm bits are set to 1 table 5.32 sci and scif timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. *1 max. *1 unit *1 test conditions sci input clock cycle asynchronous t scyc 4 ? t pbcyc figure 5.44 clock synchronous 6? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?5ns input clock fall time t sckf ?5ns output clock cycle asynchronous *2 t scyc 8?t pbcyc clock synchronous 4? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?5ns output clock fall time t sckf ?5ns transmit data delay time clock synchronous t txd ? 28 ns figure 5.45 receive data setup time clock synchronous t rxs 15 ? ns receive data hold time clock synchronous t rxh 5?ns scif input clock cycle asynchronous t scyc 4?t pacyc figure 5.44 clock synchronous 12 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?5ns input clock fall time t sckf ?5ns output clock cycle asynchronous *3 t scyc 8?t pacyc clock synchronous 4? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?5ns output clock fall time t sckf ?5ns transmit data delay time master t txd ? 10 ns figure 5.45 slave ? 4 t pacyc + 20 receive data setup time master t rxs 3 t pacyc + 20 ? ns slave t pacyc + 10 ? receive data hold time master t rxh -3 t pacyc + 5 ? ns slave 2 t pacyc + 10 ?
r01ds0173ej0100 rev.1.00 page 184 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.44 sck clock input timing figure 5.45 sci input/output timing: clock synchronous mode t sckw t sckr t sckf t scyc sckn (n = 0 to 12) t txd t rxs t rxh txdn rxdn sckn n = 0 to 12
r01ds0173ej0100 rev.1.00 page 185 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pacyc : pclka cycle note 2. we recommend using pins that have a letter (?-a?, ?-b? , etc.) to indicate group membership appended to their names as gr oups. for the rspi interface, the ac portion of the elec trical characteristics is measured for each group. table 5.33 rspi timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min.* 1 max.* 1 unit* 1 test conditions* 2 rspi rspck clock cycle master t spcyc 2 4096 t pacyc figure 5.46 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock rise/fall time output t spckr, t spckf ?5ns input ? 1 s data input setup time master t su 6 ? ns figure 5.47 to figure 5.52 slave 8.3 ? t pacyc ? data input hold time master pclka division ratio set to 1/2 t hf 0?ns pclka division ratio set to a value other than 1/2 t h t pacyc ? slave 8.3 + 2 t pacyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pacyc ssl hold time master t lag 18t spcyc slave 4 ? t pacyc data output delay time master t od ?6.3ns slave ? 3 t pacyc + 20 data output hold time master t oh 0?ns slave 0 ? successive transmission delay time master t td t spcyc + 2 t pacyc 8 t spcyc + 2 t pacyc ns slave 4 t pacyc ? mosi and miso rise/fall time output t dr, t df ?5ns input ? 1 s ssl rise/fall time output t sslr, t sslf ?5ns input ? 1 s slave access time t sa ?4t pacyc figure 5.51, figure 5.52 slave output release time t rel ?3t pacyc
r01ds0173ej0100 rev.1.00 page 186 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.46 rspi clock timing and simple spi clock timing table 5.34 simple spi timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pbcyc figure 5.46 sck clock cycle input (slave) 8 65536 sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time t su 33.3 ? ns figure 5.47 to figure 5.52 data input hold time t h 33.3 ? ns ss input setup time t lead 1?t spcyc ss input hold time t lag 1?t spcyc data output delay time t od ? 33.3 ns data output hold time t oh ?10 ? ns data rise/fall time t dr, t df ? 16.6 ns ss input rise/fall time t sslr, t sslf ? 16.6 ns slave access time t sa ?5t pacyc figure 5.51, figure 5.52 slave output release time t rel ?5t pacyc rspcka master select output rspcka slave select input t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc rspi simple spi (n = 0 to 7, 12) sckn master select output sckn slave select input
r01ds0173ej0100 rev.1.00 page 187 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.47 rspi timing (master, cpha = 0) (bit rate: pclkb division rati o set to a value other than 1/2) and simple spi timing (master, ckph = 1) figure 5.48 rspi timing (master, cpha = 0) (bit rate: pclkb divi sion ratio set to 1/2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output simple spi (n = 0 to 7, 12) t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi t h
r01ds0173ej0100 rev.1.00 page 188 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.49 rspi timing (master, cpha = 1) (bit rate: pclkb division rati o set to a value other than 1/2) and simple spi timing (master, ckph = 0) figure 5.50 rspi timing (master, cpha = 1) (bit rate: pclkb divi sion ratio set to 1/2) t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output simple spi (n = 0 to 7, 12) t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi t dr, t df t h
r01ds0173ej0100 rev.1.00 page 189 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.51 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) figure 5.52 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input rspi ssn# input sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input simple spi (n = 0 to 7, 12) ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out rspi ssn# input sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input simple spi (n = 0 to 7, 12)
r01ds0173ej0100 rev.1.00 page 190 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle note 2. we recommend using pins that have a letter (?-a?, ?-b? , etc.) to indicate group membership appended to their names as gr oups. for the qspi interface, the ac portion of the el ectrical characte ristics is measured for each group. figure 5.53 qspi clock timing figure 5.54 transmit/receive timing (cpha = 0) table 5.35 qspi timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit* 1 test conditions* 2 qspi qspclk clock cycle t qscyc 2 4080 t pbcyc figure 5.53 data input setup time t su 6.5 ? ns figure 5.54, figure 5.55 data input hold time t ih 5?ns ss setup time t lead 1.5 8.5 t qscyc ss hold time t lag 18t qscyc data output delay time t od ? 10.0 ns data output hold time t oh ?5 ? ns successive transmi ssion delay time t td 18t qscyc t qscyc qspclk output msb in msb out lsb out idle data lsb in data qssl output qspclk cpol = 0 output qspclk cpol = 1 output qmi, qio0 to qio3 input qmo, qio0 to qio3 output t lead t lag t su t ih t oh t od t td
r01ds0173ej0100 rev.1.00 page 191 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.55 transmit/receive timing (cpha = 1) msb in msb out lsb out idle data lsb in data qssl output qspclk cpol = 0 output qspclk cpol = 1 output qmi, qio0 to qio3 input qmo, qio0 to qio3 output t lead t lag t oh t od t td t su t ih
r01ds0173ej0100 rev.1.00 page 192 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note: t iiccyc : riic internal reference clock (iic ? ) cycle note 1. the value within parentheses is applicable when the value of the icmr3.nf[1:0] bits is 11b while the digital filter is e nabled by the setting icfer.nfe = 1. note 2. cb is the total capacitance of the bus lines. table 5.36 riic timing (1) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr high-drive output is selected by the driving ability control register. item symbol min.* 1, * 2 max. unit test conditions riic (standard-mode, smbus) icfer.fmpe = 0 scl input cycle time t scl 6(12) t iiccyc + 1300 ? ns figure 5.56 scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr ?1000ns scl, sda input fall time t sf ?300ns scl, sda input spike pulse removal time t sp 0 1(4) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?ns scl, sda capacitive load c b ? 400 pf riic (fast-mode) icfer.fmpe = 0 scl input cycle time t scl 6(12) t iiccyc + 600 ? ns scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 (external pull-up voltage/5.5v) 300 ns scl, sda input fall time t sf 20 (external pull-up voltage/5.5v) 300 ns scl, sda input spike pulse removal time t sp 0 1(4) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?ns scl, sda capacitive load c b ? 400 pf
r01ds0173ej0100 rev.1.00 page 193 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note: t iiccyc : riic internal reference clock (iic ? ) cycle, t pbcyc : pclkb cycle note 1. the value within parentheses is applicable when the value of the icmr3.nf[1:0] bits is 11b while the digital filter is e nabled by the setting icfer.nfe = 1. note 2. cb is the total capacitance of the bus lines. table 5.37 riic timing (2) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr high-drive output is selected by the driving ability control register. item symbol min.* 1, * 2 max. unit test conditions riic (fast-mode+) icfer.fmpe = 1 scl input cycle time t scl 6(12) t iiccyc + 240 ? ns figure 5.56 scl input high pulse width t sclh 3(6) t iiccyc + 120 ? ns scl input low pulse width t scll 3(6) t iiccyc + 120 ? ns scl, sda input rise time t sr ? 120 ns scl, sda input fall time t sf ? 120 ns scl, sda input spike pulse removal time t sp 01(4) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 120 ? ns start condition input hold time t stah t iiccyc + 120 ? ns restart condition input setup time t stas 120 ? ns stop condition input setup time t stos 120 ? ns data input setup time t sdas t iiccyc + 20 ? ns data input hold time t sdah 0?ns scl, sda capacitive load c b ? 550 pf simple iic (standard-mode) sda input rise time t sr ? 1000 ns sda input fall time t sf ? 300 ns sda input spike pulse removal time t sp 04 t pbcyc ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?ns scl, sda capacitive load c b ? 400 pf simple iic (fast-mode) scl, sda input rise time t sr ? 300 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 04 t pbcyc ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?ns scl, sda capacitive load c b ? 400 pf
r01ds0173ej0100 rev.1.00 page 194 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.56 riic bus interface input/output timing and simple iic bus interface input/output timing sda0 to sda3 scl0 to scl3 v ih v il t stah t sclh t scll p* 1 s* 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p* 1 t buf test conditions v ih = vcc 0.7, v il = vcc 0.3 v ol = 0.6v, i ol = 6ma (icfer.fmpe = 0) v ol = 0.4v, i ol = 15ma (icfer.fmpe = 1) sr* 1 note 1. s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: restart condition
r01ds0173ej0100 rev.1.00 page 195 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.57 clock input/output timing figure 5.58 transmit/receive timing (ssisckn rising synchronous) table 5.38 serial sound interface timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit test conditions ssi audio_clk input frequency t audio ?50mhz output clock cycle t o 150 64000 ns figure 5.57 input clock cycle t i 150 64000 ns clock high level t hc 60 ? ns clock low level t lc 60 ? ns clock rising time t rc ?25ns data delay time t dtr ?5 25 ns figure 5.58, figure 5.59 setup time t sr 25 ? ns hold time t htr 25 ? ns ws change edge ssidata output delay t dtrw ? 25 ns figure 5.60 ssisckn t hc t lc t rc t i , t o t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan, ssirxdn (input) ssiwsn, ssidatan, ssitxdn (output)
r01ds0173ej0100 rev.1.00 page 196 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.59 transmit/receive timing (ssisckn falling synchronous) figure 5.60 ssidata output de lay from ssiwsn change edge t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan, ssirxdn (input) ssiwsn, ssidatan, ssitxdn (output) t dtrw ssiwsn (input) ssidatan (output) msb bit output timing in slave transmission from ssiwsn with the settings of del = 1, sdta = 0, or del = 1, sdta = 1, swl[2:0] = dwl[2:0]
r01ds0173ej0100 rev.1.00 page 197 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle note 2. we recommend using pins that have a letter (?-a?, ?-b?, etc.) to indicate group membership appended to their names as gr oups. for the mmc interface, the ac portion of the elec trical characteristics is measured for each group. figure 5.61 mmc interface table 5.39 mmc host interface timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min.* 1 max. unit test conditions* 2 mmcif mmc_clk clock cycle t mmcpp 2 t pbcyc ? ns figure 5.61 mmc_clk clock high level width t mmcwh 6.5 ? ns mmc_clk clock low level width t mmcwl 6.5 ? ns mmc_clk clock rising time t mmclh ?5ns mmc_clk clock falling time t mmchl ?5ns mmc_cmd, mmc_d7 to mmc_d0 output data delay (data transfer mode) t mmcodly ?6.5 6.5 ns mmc_cmd, mmc_d7 to mmc_d0 input data setup t mmcisu 8?ns mmc_cmd, mmc_d7 to mmc_d0 input data hold t mmcih 2?ns t mmcpp t mmcwl t mmcwh t mmchl t mmclh t mmcisu t mmcih t mmcodly (max) t mmcodly (min) mmc_clk mmc_cmd, mmc_d7 to mmc_d0 input mmc_cmd, mmc_d7 to mmc_d0 output
r01ds0173ej0100 rev.1.00 page 198 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. rmii_txd_en, rmii_txd1, rmii_txd0 note 2. rmii_crs_dv, rmii_rxd1, rmii_rxd0, rmii_rx_er table 5.40 etherc timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. max. unit test conditions etherc (rmii) ref50ck cycle time t ck 20 ? ns figure 5.62 to figure 5.64 ref50ck frequency typ. 50 mhz ? ? 50 + 100ppm mhz ref50ck duty ? 35 65 % ref50ck rise/fall time t ckr/ckf 0.5 3.5 ns rmii_xxxx* 1 output delay time t co 2.5 15.0 ns rmii_xxxx* 2 setup time t su 3?ns rmii_xxxx* 2 hold time t hd 1?ns rmii_xxxx* 1, * 2 rise/fall time t r /t f 0.5 5 ns et_wol output delay time t wold 1 23.5 ns figure 5.66 etherc (mii) et_tx_clk cycle time t tcyc 40 ? ns ? et_tx_en output delay time t tend 1 20 ns figure 5.67 et_etxd0 to et_etxd3 output delay time t mtdd 120ns et_crs setup time t crss 10 ? ns et_crs hold time t crsh 10 ? ns et_col setup time t cols 10 ? ns figure 5.68 et_col hold time t colh 10 ? ns et_rx_clk cycle time t trcyc 40 ? ns ? et_rx_dv setup time t rdvs 10 ? ns figure 5.69 et_rx_dv hold time t rdvh 10 ? ns et_erxd0 to et_erxd3 setup time t mrds 10 ? ns et_erxd0 to et_erxd3 hold time t mrdh 10 ? ns et_rx_er setup time t rers 10 ? ns figure 5.70 et_rx_er hold time t resh 10 ? ns et_wol output delay time t wold 1 23.5 ns figure 5.71
r01ds0173ej0100 rev.1.00 page 199 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.62 timing with the ref50ck and rmii signals figure 5.63 rmii transmission timing figure 5.64 rmii recepti on timing (normal operation) change in signal level signal thd tsu tco tf tr tckr tckf tck signal 90% 50% 10% 70% 50% ref50ck rmii_xxxx *1 30% note 1. rmii_txd_en, rmii_txd1, rmii_txd0, rmii_crs_dv, rmii_rxd1, rmii_rxd0, rmii_rx_er change in signal level change in signal level preamble sfd data crc t co t co t ck ref50ck rmii_txd_en rmii_txd1, rmii_txd0 preamble data crc sfd tsu tsu thd thd l ref50ck rmii_crs_dv rmii_rxd1, rmii_rxd0 rmii_rx_er
r01ds0173ej0100 rev.1.00 page 200 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.65 rmii reception timing (error occurrence) figure 5.66 wol output timing (rmii) figure 5.67 mii transmission timing (normal operation) preamble data ref50ck rmii_crs_dv rmii_rxd1, rmii_rxd0 sfd xxxx rmii_rx_er tsu thd t wold ref50ck et_wol et_tx_clk et_tx_en et_etxd[3:0] et_tx_er et_crs et_col sfd data crc preamble t tend t mtdd t crss t crsh
r01ds0173ej0100 rev.1.00 page 201 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.68 mii transmission timing (conflict occurrence) figure 5.69 mii reception timing (normal operation) figure 5.70 mii reception timing (error occurrence) et_tx_clk et_tx_en et_etxd[3:0] et_tx_er et_crs et_col jam preamble t cols t colh preamble data crc sfd t rdvs t mrds t mrdh t rdvh et_rx_clk et_rx_dv et_erxd[3:0] et_rx_er preamble data sfd t rers et_rx_clk et_rx_dv et_erxd[3:0] et_rx_er xxxx t rerh
r01ds0173ej0100 rev.1.00 page 202 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.71 wol output timing (mii) t wold et_rx_clk et_wol
r01ds0173ej0100 rev.1.00 page 203 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. t pbcyc : pclkb cycle figure 5.72 pdc input clock timing figure 5.73 pdc output clock timing table 5.41 pdc timing conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min.* 1 max. unit test conditions pdc pixclk input cycle time t pixcyc 37 ? ns figure 5.72 pixclk input high pulse width t pixh 10 ? ns pixclk input low pulse width t pixl 10 ? ns pixclk rising time t pixr ?5ns pixclk falling time t pixf ?5ns pcko output cycle time t pckcyc 2 t pbcyc ? ns figure 5.73 pcko output high pulse width t pckh (t pckcyc ? t pckr ? t pckf )/2 ? 3 ? ns pcko output low pulse width t pckl (t pckcyc ? t pckr ? t pckf )/2 ? 3 ? ns pcko rising time t pckr ?5ns pcko falling time t pckf ?5ns vsynv/hsync input setup time t syncs 10 ? ns figure 5.74 vsynv/hsync input hold time t synch 5?ns pixd input setup time t pixds 10 ? ns pixd input hold time t pixdh 5?ns t pixcyc t pixh t pixf t pixl t pixr pixclk input t pckcyc t pckh t pckf t pckl t pckr pcko pin output
r01ds0173ej0100 rev.1.00 page 204 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.74 pdc ac timing pixclk vsync hsync pixd7 to pixd0 t syncs t syncs t pixds t pixdh t synch t synch
r01ds0173ej0100 rev.1.00 page 205 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.4 usb characteristics figure 5.75 dp and dm output timing (low speed) figure 5.76 test circuit (low speed) table 5.42 on-chip usb low speed (host only) ch aracteristics (dp and dm pin characteristics) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 3.0 to 3.6 v, 3.0 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, usba_rref = 2.2 k ? 1%, usbmclk = 20/24 mhz, uclk = 48 mhz, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr item symbol min. typ. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? ? v input low level voltage v il ??0.8v differential input sensitivity v di 0.2 ? ? v | dp ? dm | differential common mode range v cm 0.8 ? 2.5 v output characteristics output high level voltage v oh 2.8 ? 3.6 v i oh = ?200 a output low level voltage v ol 0.0 ? 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 ? 2.0 v figure 5.75 rise time t lr 75 ? 300 ns fall time t lf 75 ? 300 ns rise/fall time ratio t lr / t lf 80 ? 125 % t lr / t lf pull-down characteristics dp/dm pull-down resistance (when the host controller function is selected) r pd 14.25 ? 24.80 k ? dp, dm t lf t lr 90% 10% 10% 90% v crs observation point 200 pf to 600 pf dp dm 200 pf to 600 pf 1.5 k ? 3.6 v usb0: 27 ? usba: not necessary
r01ds0173ej0100 rev.1.00 page 206 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.77 dp and dm ou tput timing (full-speed) figure 5.78 test circuit (full-speed) table 5.43 on-chip usb full-speed characteristics (dp and dm pin characteristics) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 3.0 to 3.6 v, 3.0 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, usba_rref = 2.2 k ? 1%, usbmclk = 20/24 mhz, uclk = 48 mhz, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr item symbol min. typ. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? ? v input low level voltage v il ?? 0.8v differential input sensitivity v di 0.2 ? ? v | dp ? dm | differential common mode range v cm 0.8 ? 2.5 v output characteristics output high level voltage v oh 2.8 ? 3.6 v i oh = ?200 a output low level voltage v ol 0.0 ? 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 ? 2.0 v figure 5.77 rise time t fr 4 ? 20 ns fall time t ff 4 ? 20 ns rise/fall time ratio t fr / t ff 90 ? 111.11 % t fr / t ff output resistance z drv 28 ? 44 ? usbfs: rs = 27 ? included 40.5 ? 49.5 ? usba: rs not necessary (physet.repsel[1:0] = 01b and physet.hseb = 0) pull-up and pull-down characteristics dp pull-up resistance (when the function controller function is selected) r pu 0.900 ? 1.575 k ? idle state 1.425 ? 3.090 k ? at transmission and reception dp/dm pull-down resistance (when the host controller function is selected) r pd 14.25 ? 24.80 k ? dp, dm t ff t fr 90% 10% 10% 90% v crs observation point 50 pf 50 pf dp dm usb0: 27 ? usba: not necessary
r01ds0173ej0100 rev.1.00 page 207 of 230 jul 31, 2014 rx64m group 5. electrical characteristics table 5.44 battery charge characteristics (usba only) conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, usba_rref = 2.2 k ? 1%, usbmclk = 20/24 mhz, pclka = 8 to 120 mhz, pclkb = 8 to 60 mhz, t a = t opr item symbol min. max. unit test conditions d+ sink current i dp_sink 25 175 a d- sink current i dm_sink 25 175 a dcd source current i dp_src 713 a data detection voltage v dat_ref 0.25 0.4 v d+ source voltage v dp_src 0.5 0.7 v output current = 250 a d- source voltage v dm_src 0.5 0.7 v output current = 250 a
r01ds0173ej0100 rev.1.00 page 208 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.5 a/d conversion characteristics note: the above specification val ues apply when there is no access to the exter nal bus during a/d conver sion. if access proceeds during a/d conversion, values may not fall within the above ranges. note 1. the conversion time includes the sampling time and the co mparison time. as the test conditions, the number of sampling s tates is indicated. note 2. the value in parentheses indicates the sampling time. table 5.45 12-bit a/d (unit 0) conversion characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclkb = pclkc = 1 mhz to 60 mhz, t a = t opr item min. typ. max. unit test conditions resolution 8 ? 12 bit analog input capacitance ? ? 30 pf channel-dedicated sample-and-hold circuits in use (an000 to an002) conversion time* 1 (operation at pclk = 60 mhz) permissible signal source impedance (max.) = 1.0 k ? 1.06 (0.40 + 0.25) * 2 ?? s ? sampling of channel- dedicated sample-and- hold circuits in 24 states ? sampling in 15 states offset error ? 1.5 3.5 lsb an000 to an002 = 0.25 v full-scale error ? 1.5 3.5 lsb an000 to an002 = vrefh0 - 0.25 v quantization error ? 0.5 ? lsb absolute accuracy ? 2.5 5.5 lsb dnl differential nonlinearity error ? 1.0 2.0 lsb inl integral nonlinearity error ? 1.5 3.0 lsb holding characteristics of sample-and- hold circuits ??20 s dynamic range 0.25 ? vrefh 0 ? 0.25 v channel-dedicated sample-and-hold circuits not in use (an000 to an007) conversion time* 1 (operation at pclk = 60 mhz) permissible signal source impedance (max.) = 1.0 k ? 0.48 (0.267) * 2 ?? s sampling in 16 states offset error ? 1.0 2.5 lsb full-scale error ? 1.0 2.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 2.0 4.5 lsb dnl differential nonlinearity error ? 0.5 1.5 lsb inl integral nonlinearity error ? 1.0 2.5 lsb
r01ds0173ej0100 rev.1.00 page 209 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note: the above specification val ues apply when there is no access to the exter nal bus during a/d conver sion. if access proceeds during a/d conversion, values may not fall within the above ranges. note 1. the conversion time includes the sampling time and the co mparison time. as the test conditions, the number of sampling s tates is indicated. note 2. the value in parentheses indicates the sampling time. table 5.46 12-bit a/d (unit 1) conversion characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v , pclkb = pclkd = 1 mhz to 60 mhz, t a = t opr item min. typ. max. unit test conditions resolution 8 ? 12 bit conversion time* 1 (operation at pclk = 60 mhz) permissible signal source impedance (max.) = 1.0 k ? 0.88 (0.667) * 2 ?? s sampling in 40 states analog input capacitance ? ? 30 pf offset error ? 2.0 3.5 lsb full-scale error ? 2.0 3.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 4.0 6.0 lsb dnl differential nonlinearity error ? 1.5 2.5 lsb inl integral nonlinearity error ? 2.0 3.5 lsb table 5.47 a/d internal reference voltage characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, pclkb = pclkd = 60 mhz, t a = t opr item min. typ. max. unit test conditions a/d internal reference voltage 1.20 1.25 1.30 v
r01ds0173ej0100 rev.1.00 page 210 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.6 d/a conversion characteristics 5.7 temperature sensor characteristics table 5.48 d/a conversion characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item min. typ. max. unit test conditions resolution 12 12 12 bit without amp output absolute accuracy ? ? 6.0 lsb 2-m ? resistive load 10-bit conversion dnl differential nonlinearity error ? 1.0 2.0 lsb 2-m ? resistive load ro output resistance ? 7.5 ? k ? conversion time ? ? 3.0 s 20-pf capacitive load with amp output resistive load 5 ? ? k ? capacitive load ? 50 pf output voltage range 0.2 ? avcc1 ? 0.2 v dnl differential nonlinearity error ? 1.0 2.0 lsb inl integral nonlinearity error ? 2.0 4.0 lsb conversion time ? ? 4.0 s table 5.49 temperature sensor characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item min. typ. max. unit test conditions relative accuracy D 1 D c temperature slope D 3.8 D mv/c output voltage (at 25c) D 1.21 D v temperature sensor start time DD 30 s sampling time DD 4.15 s adsstrt.sst[7:0] = 250 states
r01ds0173ej0100 rev.1.00 page 211 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.8 power-on reset circuit and voltage detecti on circuit characteristics note: the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det1, and v det2 for the por/ lvd. note 1. the low power consumption function is disabled and deepcut[1:0] = 00b or 01b. note 2. the low power consumption f unction is enabled and deepcut[1:0] = 11b. note 3. the voltage of vcc = avcc0 = avcc1 when lvd1 is enabled must be set to at least 80 mv above the maximum value of the voltage detection 1 level (v det1_1, 2, 3 ) selected by the lvdlvlr.lvd1lvl[3:0] bits. similarly, the voltage of vcc = avcc0 = avcc1 when lvd2 is enabled must be set to at least 80 mv above the maximum value of the voltage detection 2 level (v det2_1, 2, 3 ) selected by the lvdlvlr.lvd2lvl[3:0] bits. table 5.50 power-on reset circuit and voltage detection circuit characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) low power consumption function disabled* 1 v por 2.5 2.6 2.7 v figure 5.79 low power consumption function enabled* 2 2.0 2.35 2.7 voltage detection circuit (lvd0) v det0_1 2.84 2.94 3.04 figure 5.80 v det0_2 2.77 2.87 2.97 v det0_3 2.70 2.80 2.90 voltage detection circuit (lvd1) v det1_1 2.89 2.99 3.09 figure 5.81 v det1_2 2.82 2.92 3.02 v det1_3 2.75 2.85 2.95 voltage detection circuit (lvd2) v det2_1 2.89 2.99 3.09 figure 5.82 v det2_2 2.82 2.92 3.02 v det2_3 2.75 2.85 2.95 internal reset time power-on reset time t por ? 4.6 ? ms figure 5.79 lvd0 reset time t lvd0 ? 0.70 ? figure 5.80 lvd1 reset time t lvd1 ? 0.57 ? figure 5.81 lvd2 reset time t lvd2 ? 0.57 ? figure 5.82 minimum vcc down time t voff 200 ? ? s figure 5.79, figure 5.80 response delay time t det ? ? 200 s figure 5.79 to figure 5.82 lvd operation stabilization time (after lvd is enabled)* 3 t d(e-a) ??10 s figure 5.81, figure 5.82 hysteresis width (lvd1 and lvd2) v lvh ?80?mv
r01ds0173ej0100 rev.1.00 page 212 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.79 power-on reset timing figure 5.80 voltage detection circuit timing (v det0 ) internal reset signal (low is valid) vcc t voff t det t por t det t por t det v por t voff t lvd0 t det v det0 vcc internal reset signal (low is valid) t det
r01ds0173ej0100 rev.1.00 page 213 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.81 voltage detection circuit timing (v det1 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (low is valid) when lvd1rn = l when lvd1rn = h v lvh t lvd1
r01ds0173ej0100 rev.1.00 page 214 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.82 voltage detection circuit timing (v det2 ) t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (low is valid) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0173ej0100 rev.1.00 page 215 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.9 oscillation stop detection timing figure 5.83 oscillation stop detection timing 5.10 battery backup function characteristics note: the vcc-off period for starting power supply switching indicate s the period in which vcc is below the minimum value of the voltage level for switching to battery backup (v detbatt ). figure 5.84 battery backup function characteristics table 5.51 oscillation stop detection circuit characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.83 table 5.52 battery backup function characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, v batt = 2.0 to 3.6 v, t a = t opr item symbol min. typ. max. unit test conditions voltage level for switching to battery backup v detbatt 2.50 2.60 2.70 v figure 5.84 lower-limit v batt voltage for power supply switching due to vcc voltage drop v battsw 2.70 ? ? vcc-off period for starting power supply switching t voffbatt 200 ? ? s t dr main clock or pll clock ostdsr.ostdf loco clock iclk vcc t voffbatt v detbatt v battsw v batt vcc supply v batt supply vcc supply backup power area
r01ds0173ej0100 rev.1.00 page 216 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.11 flash memory characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 256-byte programming is performed 32 times for different addresses in 8-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. this is the minimum number of times to guarantee all t he characteristics after reprogramming (guaranteed range is from 1 to the value of the minimum value). note 3. this shows the characteristics when reprogramming is performed within the sp ecified range, including the minimum value. table 5.53 code flash memory characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v temperature range for programming/erasure: t a = t opr item symbol fclk = 4 mhz 20 mhz fclk 60 mhz unit min. typ. max. min. typ. max. programming time n pec ? 100 times 256 bytes t p256 ?tbdtbd? 2 6 ms 8 kbytes t p8k ? tbd tbd ? 50 90 ms 32 kbytes t p32k ? tbd tbd ? 200 360 ms programming time n pec > 100 times 256 bytes t p256 ?tbdtbd? 2.4 7.2ms 8 kbytes t p8k ? tbd tbd ? 60 108 ms 32 kbytes t p32k ? tbd tbd ? 240 432 ms erasure time n pec ? 100 times 8 kbytes t e8k ? tbd tbd ? 50 120 ms 32 kbytes t e32k ? tbd tbd ? 200 480 ms erasure time n pec > 100 times 8 kbytes t e8k ? tbd tbd ? 60 144 ms 32 kbytes t e32k ? tbd tbd ? 240 576 ms reprogramming/erasure cycle* 1 n pec 1000* 2 ? ? 1000* 2 ??times suspend delay time during programming t spd ? ? tbd ? ? 120 s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? tbd ? ? 120 s second suspend delay time during erasure (in suspend priority mode) t sesd2 ??tbd??1.7ms suspend delay time during erasure (in erasure priority mode) t seed ??tbd??1.7ms forced stop command t fd ??tbd??20 s data hold time* 3 t drp 10 ? ? 10 ? ? year fcu reset time t fcur 35 ? ? 35 ? ? s
r01ds0173ej0100 rev.1.00 page 217 of 230 jul 31, 2014 rx64m group 5. electrical characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000), erasing can be performed n times for each block. for instance, when 4-byte programming is performed 512 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. this is the minimum number of times to guarantee all t he characteristics after reprogramming (guaranteed range is from 1 to the value of the minimum value). note 3. this shows the characteristics when reprogramming is performed within the sp ecified range, including the minimum value. table 5.54 data flash memory characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, temperature range for programming/erasure: t a = t opr item symbol fclk = 4 mhz 20 mhz fclk 60 mhz unit min. typ. max. min. typ. max. programming time 4 bytes t dp4 ?tbdtbd? 0.3 1.7ms erasure time 64 bytes t de64 ?tbdtbd? 3 10 ms blank check time 4 bytes t dbc4 ??tbd??30 s reprogramming/erasure cycle* 1 n dpec 100000 * 2 ? ? 100000 * 2 ??? suspend delay time during programming t dspd ? ? tbd ? ? 120 s first suspend delay time during erasure (in suspend priority mode) t dsesd1 ? ? tbd ? ? 120 s second suspend delay time during erasure (in suspend priority mode) t dsesd2 ? ? tbd ? ? 300 s suspend delay time during erasing (in erasure priority mode) t dseed ? ? tbd ? ? 300 s forced stop command t fd ?tbd???20 s data hold time* 3 t ddrp 10 ? ? 10 ? ? ?
r01ds0173ej0100 rev.1.00 page 218 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.85 flash memory programming/erasure suspension timing fcu command fstatr0.frdy programming pulse ? suspension during programming fcu command fstatr0.frdy erasure pulse ? suspension during erasure in suspend priority mode fcu command fstatr0.frdy erasure pulse ? suspension during erasure in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0173ej0100 rev.1.00 page 219 of 230 jul 31, 2014 rx64m group 5. electrical characteristics 5.12 boundary scan figure 5.86 boundary scan tck timing figure 5.87 boundary scan trst# timing table 5.55 boundary scan characteristics conditions: vcc = avcc0 = avcc1 = vcc_usb = v batt = 2.7 to 3.6 v, 2.7 vrefh0 avcc0, vcc_usba = avcc_usba = 3.0 to 3.6 v, vss = avss0 = avss1 = vrefl0 = vss_usb = vss1_usba = vss2_usba = pvss_usba = avss_usba = 0 v, t a = t opr output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, c = 30 pf high-drive output is selected by the driving ability control register. item symbol min. typ. max. unit test conditions tck clock cycle time t tckcyc 100 DD ns figure 5.86 tck clock high pulse width t tckh 45 DD ns tck clock low pulse width t tckl 45 DD ns tck clock rise time t tckr DD 5ns tck clock fall time t tckf DD 5ns trst# pulse width t trstw 20 DD t tckcyc figure 5.87 tms setup time t tmss 20 DD ns figure 5.88 tms hold time t tmsh 20 DD ns tdi setup time t tdis 20 DD ns tdi hold time t tdih 20 DD ns tdo data delay time t tdod DD 40 ns tck t tckcyc t tckh t tckf t tckl t tckr res# trst# tck t trstw
r01ds0173ej0100 rev.1.00 page 220 of 230 jul 31, 2014 rx64m group 5. electrical characteristics figure 5.88 boundary scan input/output timing t tmss tck tms tdi tdo t tmsh t tdis t tdih t tdod
r01ds0173ej0100 rev.1.00 page 221 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 177-pin tflga (ptlg0177ka-a) e e s b a r p 15 14 13 12 11 10 9 n m l k j index mark (laser mark) x4 v ab s ab s y s 8 7 6 5 4 3 2 1 b c d e f g h a s a w s w b z e z d a e d ptlg0177ka-a 177f0e-a 0.2g p-tflga177-8x8-0.50 0.15 v 0.20 w 0.08 0.39 0.34 0.29 max nom min dimension in millimeters symbol reference 8.0 d 8.0 e 1.05 a x 0.5 e 0.08 y b 1 b 0.21 0.25 0.29 0.5 z d z e 0.5 mass[typ.] renesas code jeita package code previous code b 1 b m m
r01ds0173ej0100 rev.1.00 page 222 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure b 176-pin lfbga (plbg0176ga-a)
r01ds0173ej0100 rev.1.00 page 223 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure c 176-pin lqfp (plqp0176kb-a) note ) 1 . d i m en s ion s " * 1 " a n d " * 2 " d o not in c lu d e m ol d fl as h. 2 . d i m en s ion " * 3 " d oe s not in c lu d e t r i m off s et. d i mens i on i n m illi meters reference symbo l m i n n om max b p b 1 c 1 c * 2 e h e * 1 d h d t erm i na l cross sect i on deta il f c l f m s s y e l 1 a 1 a 2 a x b p * 3 i ndex mark z d z e 1 176 133 132 89 88 4 5 44 23 . 92 4. 02 4. 1 23 . 92 4. 0 1 .4 2 4. 1 25 . 826 . 026 . 2 25 . 826 . 026 . 2 0 . 05 0 . 1 0 . 18 0 . 15 0 . 15 0 . 20 0 . 25 0 . 09 0 . 1 4 5 0 . 125 0 . 5 1 . 0 1 . 25 1 . 25 0 8 0 . 20 0 . 35 0 . 50 . 65 0 . 08 0 . 10 1 . 7 j eit a package code r ene sas code prev i ous code mass [t yp .] p -lfqf p176 - 2 4 x2 4- 0 . 50 p lq p0176 k b - a 176p6 q- a /f p - 176 e/f p - 176 ev 1 . 8g l 1 c 1 b 1 a 1 a 2 a b p h e e d h d z e z d l y x e c
r01ds0173ej0100 rev.1.00 page 224 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure d 145-pin tflga (ptlg0145ka-a) 0.5 z e z d 0.5 0.29 0.25 0.21 b b 1 y 0.08 e 0.5 x a 1.05 e7.0 d7.0 reference symbol dimension in millimeters min nom max 0.29 0.34 0.39 0.08 w 0.20 v 0.15 ptlg0145ka-a 145f0g p-tflga145-7x7-0.50 0.1g mass[typ.] renesas code jeita package code previous code 13 12 11 10 9 n m l k j index mark (laser mark) x4 v ab a b s ab s s y s 8 7 6 5 4 3 2 1 b c d e f g h a s a w s w b z e z d a e e e d b 1 m b m
r01ds0173ej0100 rev.1.00 page 225 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure e 144-pin lqfp (plqp0144ka-a) t erm i na l cross sect i on b 1 c 1 b p c 1 . 0 0 . 125 0 . 20 1 . 25 1 . 25 0 . 08 0 . 20 0 . 1 4 5 0 . 09 0 . 27 0 . 22 0 . 17 max n om m i n d i mens i on i n m illi meters symbo l reference 20 . 1 20 . 0 19 . 9 d 20 . 1 20 . 0 19 . 9 e 1 .4 a 2 22 . 2 22 . 0 21 . 8 22 . 2 22 . 0 21 . 8 1 . 7 a 0 . 15 0 . 1 0 . 05 0 . 65 0 . 5 0 . 35 l x 8 0 c 0 . 5 e 0 . 10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p -lfqf p1 44- 20x20 - 0 . 50 1 . 2g mass [t yp .] 1 44 p6 q- a / f p - 1 44l / f p - 1 44lv p lq p01 44k a - a r ene sas code j eit a package code prev i ous code f 1 36 37 72 73 108 109 1 44 * 1 * 2 * 3 x i ndex mark h e e d h d b p z d z e deta il f c a l a 1 a 2 l 1 2 . 1 . d i m en s ion s " * 1 " a n d " * 2 " d o not in c lu d e m ol d fl as h. note ) d i m en s ion " * 3 " d oe s not in c lu d e t r i m off s et. e y s s
r01ds0173ej0100 rev.1.00 page 226 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure f 100-pin tflga (ptlg0100ja-a) p-tflga100-7x7-0.65 0.1g mass[typ.] 100f0g ptlg0100ja-a renesas code jeita package code previous code 0.15 v 0.20 w 0.08 0.485 0.435 0.385 max nom min dimension in millimeters symbol reference 7.0 d 7.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 0.575 z d z e 0.575 index mark b w s w a s a h g f e d c b 12345678 ys s a v 4 (laser mark) index mark j k 910 d e e e a z d z e b b b 1 ms ab ms ab
r01ds0173ej0100 rev.1.00 page 227 of 230 jul 31, 2014 rx64m group appendix 1. package dimensions figure g 100-pin lqfp (plqp0100kb-a) t erm i na l cross sect i on b 1 c 1 b p c 2 . 1 . d i m en s ion s " * 1 " a n d " * 2 " d o not in c lu d e m ol d fl as h. note ) d i m en s ion " * 3 " d oe s not in c lu d e t r i m off s et. i ndex mark x 125 26 50 51 75 76 100 f * 1 * 3 * 2 z e z d e d h d h e b p deta il f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0 . 08 e 0 . 5 c 0 8 x l 0 . 35 0 . 5 0 . 65 0 . 05 0 . 1 0 . 15 a 1 . 7 15 . 816 . 016 . 2 15 . 816 . 016 . 2 a 2 1 .4 e 13 . 91 4. 01 4. 1 d 13 . 91 4. 01 4. 1 reference symbo l d i mens i on i n m illi meters m i n n om max 0 . 15 0 . 20 0 . 25 0 . 09 0 . 1 4 5 0 . 20 0 . 08 1 . 0 1 . 0 0 . 18 0 . 125 1 . 0 prev i ous code j eit a package code r ene sas code p lq p0100 k b - a 100p6 q- a / f p - 100 u / f p - 100 uv mass [t yp .] 0 . 6g p -lfqf p100 - 1 4 x1 4- 0 . 50 e y s s
r01ds0173ej0100 rev.1.00 page 228 of 230 jul 31, 2014 rx64m group revision history revision history rx64m group datasheet rev. date description page summary 0.90 feb 28, 2014 ? first edition, issued 1.00 jul 31, 2014 summary 1 data transfer, changed 1. overview ? finec (pin), deleted 2 table 1.1 outline of specifications (1/9), changed 3 table 1.1 outline of specifications (2/9), changed 6 table 1.1 outline of specifications (5/9), changed 7 table 1.1 outline of specifications (6/9), changed 8 table 1.1 outline of specifications (7/9), changed 9 table 1.1 outline of specifications (8/9), changed 10 table 1.1 outline of specifications (9/9), changed 16 figure 1.1 how to read the product part number, changed 19 table 1.4 pin functions (2/8), changed 20 table 1.4 pin functions (3/8), changed 25 table 1.4 pin functions (8/8), note added 2. cpu, added 3. address space, added 4. i/o registers, added 5. electrical characteristics, added appendix 1. package dimensions, added all trademarks and registered trademarks are the property of thei r respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accordance with the dire ctions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-ku, seoul, 135-920, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2014 renesas electronics corporation. all rights reserved. colophon 4.0

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